• Title/Summary/Keyword: Wafer Fabrication

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Fabrication of the Microchannel Integrated with the Inner Sensors for Accurate Measuring Fluid Temperature (유체의 정확한 온도 측정을 위하여 내부 센서를 집적한 마이크로채널 제작)

  • Park, Ho-Jun;Im, Geun-Bae;Son, Sang-Yeong;Song, In-Seop;Park, Jeong-Ho
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.51 no.9
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    • pp.449-454
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    • 2002
  • A rectangular straight microchannel, integrated with the resistance temperature detectors(RTDs) for temperature sensing and a micro-heater for generating the Temperature gradient along the channel, was fabricated. Its dimension is 57${\mu}{\textrm}{m}$(H)$\times$200${\mu}{\textrm}{m}$(W)$\times$48,050${\mu}{\textrm}{m}$(L), and RTDs were placed at the inner-channel wall. Si wafer was used as a substrate. For the fabrication of RTDs, 5300$\AA$ thick Pt/Ti layer was sputtered on a Pyrex glass wafer. Finally, the glass wafer was bonded with Si wafer by anodic bonding, so that the RTDs are located inside the microchannel. Temperature coefficient of resistance(TCR) values of the fabricated Pt-RTDs were 2800~2950ppm$^{\circ}C$ and the variation of TCR value In the range of O~10$0^{\circ}C$ was less than 0.3%. Therefore, it was proved that the fabricated Pt-RTDs without annealing were excellent as temperature sensors. The temperature distribution in the microchannel was investigated as a function of mass flow rate and heating power. The temperature increase rate diminished with decreasing the applied power and increasing the mass flow rate. It was confirmed from the comparison with the simulation results that the temperature measured inside the microchannel is more accurate than measuring the temperature measured at the outer wall. The proposed temperature sensing method and microchannel are expected to be useful in microfluidics researches.

Fabrication and Chracteristics of Cutting Cell with Various Laser Conditions (다양한 레이저 조건에 따른 컷팅셀 제작 및 특성 분석)

  • Park, Jeong Eun;Kim, Dong Sik;Choi, Won Seok;Jang, Jae Joon;Lim, Dong gun
    • Journal of the Korean Solar Energy Society
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    • v.39 no.3
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    • pp.9-17
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    • 2019
  • Laser cutting cell of solar cells can achieve high voltage and efficiency through more array than conventional 6 inch cell compared to same area. In this study, we fabricated c-Si cutting cell with various lasers and laser conditions such as power, speed, and number of times. In the case of picosecond laser, excellent surface characteristics were obtained due to small surface defects and low thermal damage at the output of 20W and the speed of 100 mm/s. However, it is not possible to fabricate a cutting cell having good characteristics due to nonuniform cutting inside the wafer when the processing for forming a cutting cell is not sufficiently performed. For nanosecond lasers, the best wafer characteristics were obtained for fabrication of excellent cutting cells at a frequency of 500 kHz and a laser speed of 100 mm/s. However, the nanosecond laser has not been processed sufficiently in the condition of a number of times. As a result, it was confirmed that the wafer thickness was cut by $63{\mu}m$ of the cell thickness of $170{\mu}m$ in the condition of five times of laser process. It was found that more than 30% of the wafer thickness had to be processed to fabricate the cutting cell. After cutting the 6-inch cell having the voltage of 0.65 V, we obtained the voltage of about 0.63 V.

The Simulation and Forecast Model for Human Resources of Semiconductor Wafer Fab Operation

  • Tzeng, Gwo-Hshiung;Chang, Chun-Yen;Lo, Mei-Chen
    • Industrial Engineering and Management Systems
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    • v.4 no.1
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    • pp.47-53
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    • 2005
  • The efficiency of fabrication (fab) operation is one of the key factors in order for a semiconductor manufacturing company to stay competitive. Optimization of manpower and forecasting manpower needs in a modern fab is an essential part of the future strategic planing and a very important to the operational efficiency. As the semiconductor manufacturing technology has entered the 8-inch wafer era, the complexity of fab operation increases with the increase of wafer size. The wafer handling method has evolved from manual mode in 6-inch wafer fab to semi-automated or fully automated factory in 8-inch and 12-inch wafer fab. The distribution of manpower requirement in each specialty varied as the trend of fab operation goes for downsizing manpower with automation and outsourcing maintenance work. This paper is to study the specialty distribution of manpower from the requirement in a typical 6-inch, 8-inch to 12-inch wafer fab. The human resource planning in today’s fab operation shall consider many factors, which include the stability of technical talents. This empirical study mainly focuses on the human resource planning, the manpower distribution of specialty structure and the forecast model of internal demand/supply in current semiconductor manufacturing company. Considering the market fluctuation with the demand of varied products and the advance in process technology, the study is to design a headcount forecast model based on current manpower planning for direct labour (DL) and indirect labour (IDL) in Taiwan’s fab. The model can be used to forecast the future manpower requirement on each specialty for the strategic planning of human resource to serve the development of the industry.

Bottleneck Scheduling for Cycletime Reduction in Semiconductor Fabrication Line (반도체 FAB공정의 사이클타임 단축을 위한 병목일정계획)

  • 이영훈;김태헌
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 2001.10a
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    • pp.298-301
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    • 2001
  • In semiconductor manufacturing, wafer fabrication is the most complicated and important process, which is composed of several hundreds of process steps and several hundreds of machines involved. The productivity of the manufacturing mainly depends on how well they control balance of WIP flow to achieve maximal throughput under short manufacturing cycle time. In this paper mathematical formulation is suggested for the stepper scheduling, in which cycle time reduction and maximal production is achieved.

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Fabrication and Test Results of Superconducting Magnet for Crystal Growing System (단결정 성장용 초전도 마그네트의 제작 및 성능평가)

  • 심기덕;진홍범;최석진;김경한;한호한;김형진;이봉근;권영길
    • Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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    • 2002.02a
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    • pp.374-377
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    • 2002
  • Magnetic field is necessary to control the convection of melted silicon and to improve the quality of the wafer in the 12inch silicon wafer growing process. Nowadays, superconducting magnet is used in this process. We fabricated and tested a saddle shaped superconducting magnet for 8inch silicon wafer growing system. And the protection circuits for HTS current lead and superconducting coil are designed and manufactured. In this paper, their manufacturing process and test results are introduced.

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Fabrication of Micro Mirror Array for Small Form Factor Optical Pick-up by Micro UV-Molding (마이크로 UV성형을 통한 초소형 광픽업용 마이크로 미러 어레이 제작)

  • Choi Yong;Lim Jiseok;Kim Seokmin;Sohn Jin-Seung;Kim Hae-Sung;Kang Shinill
    • Transactions of Materials Processing
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    • v.14 no.5 s.77
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    • pp.477-481
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    • 2005
  • Wafer scale micro mirror array with high surface quality for small form factor (SFF) optical pick-up was fabricated by micro UV-molding. To replicate micro mirror array for SFF optical pick-up, a high- precision mold was fabricated using micro-machining technology. Wafer scale micro mirror array was UV-molded using the mold and then the process was optimized experimentally. The surface flatness and roughness of UV-molded micro mirror array were measured by white light scanning interferomety system and analyzed the transcribing characteristics. Finally, the measured flatness of UV-molded micro mirror away for SFF optical pick-up, which was fabricated in the optimum processing condition, was less than 70nm.

Scheduling Algorithms for Minimizing Total Weighted Flowtime in Photolithography Workstation of FAB (반도체 포토공정에서 총 가중작업흐름시간을 최소화하기 위한 스케쥴링 방법론에 관한 연구)

  • Choi, Seong-Woo
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.35 no.1
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    • pp.79-86
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    • 2012
  • This study focuses on the problem of scheduling wafer lots of several recipe(operation condition) types in the photolithography workstation in a semiconductor wafer fabrication facility, and sequence-dependent recipe set up times may be required at the photolithography machines. In addition, a lot is able to be operated at a machine when the reticle(mask) corresponding to the recipe type is set up in the photolithography machine. We suggest various heuristic algorithms, in which developed recipe selection rules and lot selection rules are used to generate reasonable schedules to minimizing the total weighted flowtime. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the total weighted flowtime of the wafer lots with ready times.

Fabrication of Wafer-scale Polystyrene (2+1) Dimensional Photonic Crystal Multilayers Via the Layer-by-layer Scooping Transfer Technique

  • Do, Yeong-Rak;O, Jeong-Rok;Lee, Gyeong-Nam
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2011.05a
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    • pp.11.1-11.1
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    • 2011
  • We have developed a simple synthetic method for fabricating a wafer-scale colloidal crystal film of 2D crystals in a 1D stack based on a combination of two simple processes : the self-assembly of polystyrene (PS) nanospheres at the water-air interface and the layer-by-layer (LbL) scooping transfer technique. The main advantage of this approach is that it allows excellent control of the thickness (at a layer level) of the crystals and the formation of a vertical crack-free layer over a wafer-scale (4 inch). We investigate the optical and morphological properties of the PhC multilayers fabricated using various mono-sized colloidal crystals (250, 300, 350, 420, 580, 720, and 850 nm), and mixed binary colloidal crystals (300/350 and 250/350 nm).

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The Effect of Hydrogen Plasma on Surface Roughness and Activation in SOI Wafer Fabrication

  • Park, Woo-Beom;Kang, Ho-Cheol;Sung, Man-Young
    • Transactions on Electrical and Electronic Materials
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    • v.1 no.1
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    • pp.6-11
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    • 2000
  • The hydrogen plasma treatment of silicon wafers in the reactive ion-etching mode was studied for the application to silicon-on-insulator wafers which were prepared using the wafer bonding technique. The chemical reactions of hydrogen plasma with surface were used for both surface activation and removal of surface contaminants. As a result of exposure of silicon wafers to the plasma, an active oxide layer was found on the surface. This layer was rendered hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposing time and power. In addition, the surface became smoother with the shorter plasma exposing time and power. The value of initial surface energy estimated by the crack propagation method was 506 mJ/㎡, which was up to about three times higher as compared to the case of conventional direct using the wet RCA cleaning method.

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Fabrication of Tip of Probe Card Using MEMS Technology (MEMS 기술을 이용한 프로브 카드의 탐침 제작)

  • Lee, Keun-Woo;Kim, Chang-Kyo
    • Journal of Institute of Control, Robotics and Systems
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    • v.14 no.4
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    • pp.361-364
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    • 2008
  • Tips of probe card were fabricated using MEMS technology. P-type silicon wafer with $SiO_2$ layer was used as a substrate for fabricating the probe card. Ni-Cr and Au used as seed layer for electroplating Ni were deposited on the silicon wafer. Line patterns for probing devices were formed on silicon wafer by electroplating Ni through mold which formed by MEMS technology. Bridge structure was formed by wet-etching the silicon substrate. AZ-1512 photoresist was used for protection layer of back side and DNB-H100PL-40 photoresist was used for patterning of the front side. The mold with the thickness of $60{\mu}m$ was also formed using THB-120N photoresist and probe tip with thickness of $50{\mu}m$ was fabricated by electroplating process.