• Korean Journal of Computational Design and Engineering
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• v.19 no.3
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• pp.214-223
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• 2014

This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1702-1703
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• 2011

MEMS 소자의 Wafer level Package 관련하여 Deep cavity를 가진 Cap Wafer와 Polymer bonding 중 cavity 단차로 인한 Polymer Patterning 및 접합 불량의 어려움을 극복할 수 있는 새로운 공정 flow를 제안하였다. Cavity를 형성할 때 사용하는 Si deep etching Mask인 기존의 Photoresist를 접합용 감광성 Polymer로 대체하고, cavity 형성 후, 별도의 추가 공정 없이 이 Polymer를 이용해 Wafer bonding을 진행하였다. 이를 통해 cavity 단차에 따른 문제를 해결함과 동시에 공정이 단순하고 제작 비용이 저렴하며, 신뢰성 있는 Wafer level Package를 구현하였다.

• Industrial Engineering and Management Systems
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• v.4 no.1
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• pp.47-53
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• 2005

The efficiency of fabrication (fab) operation is one of the key factors in order for a semiconductor manufacturing company to stay competitive. Optimization of manpower and forecasting manpower needs in a modern fab is an essential part of the future strategic planing and a very important to the operational efficiency. As the semiconductor manufacturing technology has entered the 8-inch wafer era, the complexity of fab operation increases with the increase of wafer size. The wafer handling method has evolved from manual mode in 6-inch wafer fab to semi-automated or fully automated factory in 8-inch and 12-inch wafer fab. The distribution of manpower requirement in each specialty varied as the trend of fab operation goes for downsizing manpower with automation and outsourcing maintenance work. This paper is to study the specialty distribution of manpower from the requirement in a typical 6-inch, 8-inch to 12-inch wafer fab. The human resource planning in today’s fab operation shall consider many factors, which include the stability of technical talents. This empirical study mainly focuses on the human resource planning, the manpower distribution of specialty structure and the forecast model of internal demand/supply in current semiconductor manufacturing company. Considering the market fluctuation with the demand of varied products and the advance in process technology, the study is to design a headcount forecast model based on current manpower planning for direct labour (DL) and indirect labour (IDL) in Taiwan’s fab. The model can be used to forecast the future manpower requirement on each specialty for the strategic planning of human resource to serve the development of the industry.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.1
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• pp.73-80
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• 2016

This study focuses on the formation of input release lots in a semiconductor wafer fabrication facility. After the order-lot pegging process assigns lots in the fab to orders and calculates the required quantity of wafers for each product type to meet customers' orders, the decisions on the formation of input release lots should be made to minimize the production costs of the release lots. Since the number of lots being processed in the wafer fab directly is related to the productivity of the wafer fab, the input lot formation is crucial process to reduce the production costs as well as to improve the efficiency of the wafer fab. Here, the input lot formation occurs before every shift begins in the semiconductor wafer fab. When input quantities (of wafers) for product types are given from results of the order-lot pegging process, lots to be released into the wafer fab should be formed satisfying the lot size requirements. Here, the production cost of a homogeneous lot of the same type of product is less than that of a heterogeneous lot that will be split into the number of lots according to their product types after passing the branch point during the wafer fabrication process. Also, more production cost occurs if a lot becomes more heterogeneous. We developed a multi-dimensional dynamic programming algorithm for the input lot formation problem and showed how to apply the algorithm to solve the problem optimally with an example problem instance. It is necessary to reduce the number of states at each stage in the DP algorithm for practical use. Also, we can apply the proposed DP algorithm together with lot release rules such as CONWIP and UNIFORM.

• Journal of the Korea Society for Simulation
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• v.15 no.2
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• pp.51-57
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• 2006

Production environment of semiconductor industry is shifting from 200mm wafer process to 300mm wafer process. In the new era of semiconductor industry, FAB (fabrication) Line Automation is a key issue that semiconductor industry is facing in shifting from 200mm wafer fabrication to 300mm wafer fabrication. In addition, since the semiconductor manufacturing technologies are being widely spread and market competitions are being stiffened, cost-down techniques became basis of growth. Most companies are trying to reduce average cycle time to increase productivity and delivery time. In this paper, we simulated 300mm wafer fabrication semiconductor manufacturing process by laying great emphasis on reduce average cycle time.

• Journal of Intelligence and Information Systems
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• v.9 no.1
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• pp.157-177
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• 2003

This paper presents a comprehensive and successful application of data mining methodologies to improve and predict wafer yield in a semiconductor wafer fabrication system. As the wafer fabrication process is getting more complex and the volume of technological data gathered continues to be vast, it is difficult to analyze the cause of yield deterioration effectively by means of statistical or heuristic approaches. To begin with this paper applies a clustering method to automatically identify AUF (Area Uniform Failure) phenomenon from data instead of naked eye that bad chips occurs in a specific area of wafer. Next, sequential pattern analysis and classification methods are applied to and out machines and parameters that are cause of low yield, respectively. Furthermore, radial bases function method is used to predict yield of wafers that are in process. Finally, this paper demonstrates an information system, Y2R-PLUS (Yield Rapid Ramp-up, Prediction, analysis & Up Support), that is developed in order to analyze and predict wafer yield in a korea semiconductor manufacturer.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.78.2-78
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• 1998

• Safety and Health at Work
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• v.9 no.3
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• pp.249-256
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• 2018

This article aims to provide a systematic review of the exposure assessment methods used to assign wafer fabrication (fab) workers in epidemiologic cohort studies of mortality from all causes and various cancers. Epidemiologic and exposure-assessment studies of silicon wafer fab operations in the semiconductor industry were collected through an extensive literature review of articles reported until 2017. The studies found various outcomes possibly linked to fab operations, but a clear association with the chemicals in the process was not found, possibly because of exposure assessment methodology. No study used a tiered assessment approach to identify similar exposure groups that incorporated manufacturing era, facility, fab environment, operation, job and level of exposure to individual hazardous agents. Further epidemiologic studies of fab workers are warranted with more refined exposure assessment methods incorporating both operation and job title and hazardous agents to examine the associations with cancer risk or mortality.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.401-406
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• 1988

Various types and huge volume of information such as process instructions, work-in process and parametric data are created in a wafer fabrication process and should be provided to personnels inside or outside the facility. This article describes design criteria and functional description on the information system for small-scale wafer fabrication process to accomplish paperless fab and to support efficient fab management.

• Journal of Sensor Science and Technology
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• v.29 no.5
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• pp.354-359
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• 2020

The high vacuum hermetic sealing technique ensures excellent performance of MEMS resonators. For the high vacuum hermetic sealing, the customization of anodic bonding equipment was conducted for the glass/Si/glass triple-stack anodic bonding process. Figure 1 presents the schematic of the MEMS resonator with triple-stack high-vacuum anodic bonding. The anodic bonding process for vacuum sealing was performed with the chamber pressure lower than 5 × 10^-6 mbar, the piston pressure of 5 kN, and the applied voltage was 1 kV. The process temperature during anodic bonding was 400 ℃. To maintain the vacuum condition of the glass cavity, a getter material, such as a titanium thin film, was deposited. The getter materials was active at the 400 ℃ during the anodic bonding process. To read out the electrical signals from the Si resonator, a vertical feed-through was applied by using through glass via (TGV) which is formed by sandblasting technique of cap glass wafer. The aluminum electrodes was conformally deposited on the via-hole structure of cap glass. The TGV process provides reliable electrical interconnection between Si resonator and aluminum electrodes on the cap glass without leakage or electrical disconnection through the TGV. The fabricated MEMS resonator with proposed vacuum packaging using three-layer anodic bonding process has resonance frequency and quality factor of about 16 kHz and more than 40,000, respectively.