• Proceedings of the KSME Conference
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• 2008.11b
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• pp.2511-2514
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• 2008

As the minimum feature size decreases, techniques to avoid contamination and processes to maintain clean wafer surfaces have become very important. The deposition and detachment of nanoparticles from surfaces are major problem to integrated circuit fabrication. Therefore, cleaning technology which reduces nanoparticles is essential to increase yield. Previous megasonic cleaning technology has reached the limits to reduce nanoparticles. Megasonic cleaning is one of the efficiency method to reduce contamination nanoparticle. Two major mechanisms are active in a megasonic cleaning, namely, acoustic streaming and cavitation. Acoustic streaming does not lead to sufficiently strong force to cause damage to the substrates or patterns. Sonoluminescence is a phenomenon of light emission associated with the cavitation of a bubble under ultrasound. We studied a correlation between sonoluminescence and sound pressure distribution for the minimum of pattern damage in megasonic cleaning.

• Laser Solutions
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• v.4 no.3
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• pp.22-29
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• 2001

A development of new surface clwaning technol ogies such as laser and aerosol in paeallel with the improvement of conventional wet mwthods becomes more essential in semiconductor industry due the confrontation of new challenges such as significant device shrink, environmental foralum inum do not work for copper as a new interconnection material, and more effective cleaning tools are required with decreasing the feature size less than 0.13 ㎛ as well as increasing the wafer size from 200 ㎜ to 300 ㎜. In this article, various cleaning techniques increasing laser cleaning are compared methodolgically hi order to understand their unique characteristics such as advantages and disadvantages according to the current clean ing issues. In particular, the current state of art of laser technique for semiconductors md prospects as a try cleaning method are described.

• Journal of the Semiconductor & Display Technology
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• v.15 no.4
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• pp.73-78
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• 2016

Contact pressure distribution between PVA brush and semiconductor wafer was measured by developing a test setup which could simulates the post CMP cleaning process. The test set-up used thin film type pressure sensor which could measure the pressure distribution of contact area with the resolution of $15.5ea/cm^2$. As the experimental results, it was verified that there had been severe contact pressure non-uniformity along the axis of the brush and between the adjacent projections on the brush's surface. These results should be considered when developing post CMP cleaning stage or designing the PVA brush.

• Bulletin of the Korean Chemical Society
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• v.18 no.7
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• pp.737-740
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• 1997

The influence of cyclic treatments with H2O2/DIW (1 : 10) and HF/DIW (1 : 100) on the roughness of silicon surface in the wet chemical processing was investigated by atomic force microscopy (AFM). During the step of the SC-1 cleaning, there is a large increase in roughness on the silicon surface which will result in the poor gate oxide breakdown properties. The roughness of the silicon wafer after the SC-1 cleaning step was reduced by cyclic treatments of hydrogen peroxide solution and hydrofluoric acid solution instead of HF-only cleaning. AFM images after each step clearly illustrated that the average roughness of silicon surface after three times treatments with H2O2 and HF solutions was reduced by 10 times compared with that after the SC-1 cleaning step.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.21-27
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• 2023

In this article, a plate-type megasonic cleaning system with cooling pins is proposed for the sliced ingot, which is a raw material of silicon (Si) wafers. The megasonic system is operated with a lead zirconate titanate (PZT) actuator, which has high electric resistance, thus when it is being operated, it dissipates much heat. So this article proposes a megasonic system with cooling pins. In the design process, finite element analysis was performed and the results were used for the design of the waveguide. The frequency with the maximum impedance value was 998 kHz, which agreed well with the measured value of 997 kHz with 0.1 % error. Based on the results, the 1 MHz waveguide was fabricated. Acoustic pressures were measured, and analyzed. Finally, cleaning tests were performed, and 90 % particle removal efficiency (PRE) was achieved over 10 W power. These results imply that the developed 1 MHz megasonic will effectively clean sliced ingot wafer surfaces.

• Korean Journal of Materials Research
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• v.24 no.12
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• pp.682-688
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• 2014

Physical and chemical changes in a polished wafer and in $2.5{\mu}m$ & $4{\mu}m$ epitaxially grown Si layer wafers (Epilayer wafer) after surface treatment were investigated. We characterized the influence of surface treatment on wafer properties such as surface roughness and the chemical composition and bonds. After each surface treatment, the physical change of the wafer surface was evaluated by atomic force microscopy to confirm the surface morphology and roughness. In addition, chemical changes in the wafer surface were studied by X-ray photoemission spectroscopy measurement. Changes in the chemical composition were confirmed before and after the surface treatment. By combined analysis of the physical and chemical changes, we found that diluted hydrofluoric acid treatment is more effective than buffered oxide etching for $SiO_2$ removal in both polished and Epi-Layer wafers; however, the etch rate and the surface roughness in the given treatment are different among the polished $2.5{\mu}m$ and $4{\mu}m$ Epi-layer wafers in spite of the identical bulk structural properties of these wafers. This study therefore suggests that independent surface treatment optimization is required for each wafer type, $2.5{\mu}m$ and $4{\mu}m$, due to the meaningful differences in the initial surface chemical and physical properties.

• Journal of Korea Multimedia Society
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• v.16 no.6
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• pp.782-794
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• 2013

This paper proposes the wafer position recognition algorithm using camera. First, for eliminating the image distortions caused by the illumination and the irregular camera position, the wafer image is restored as a circle through projective transformation. Next, we use edge detection algorithm to extract the wafer's edge and then apply Generalized Symmetry Transform(GST) to extract a circle. The GST evaluates symmetry between two points by combining a distance weight function, a phase weight function, and a logarithmic mapping of the points' intensities and detecting interest regions. Trough several experiments, we found out the proposed method is able to prevent the cleaning system and the wafer from damaging.

• Journal of the Korean Vacuum Society
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• v.9 no.2
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• pp.102-109
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• 2000

It is difficult to meet the cleanliness requirement of $10^{10}/\textrm{cm}^2$ for the giga level device fabrication with mechanical cleaning techniques like scrubbing which is widely used to remove the particles generated during Chemical Mechanical Polishing (CMP) processes. Therefore, the second cleaning process is needed to remove metallic contaminants which were not completely removed during the mechanical cleaning process. In this paper the experimental results for the removal of the metallic contaminants existing on the wafer surface using remote plasma $H_2$ cleaning and UV/$O_3$ cleaning techniques are reported. In the remote plasma $H_2$ cleaning the efficiency of contaminants removal increases with decreasing the plasma exposure time and increasing the rf-power. Also the optimum process conditions for the removal of K, Fe and Cu impurities which are easily found on the wafer surface after CMP processes are the plasma exposure time of 1min and the rf-power of 100 W. The surface roughness decreased by 30-50 % after remote plasma $H_2$ cleaning. On the other hand, the highest efficiency of K, Fe and Cu impurities removal was achieved for the UV exposure time of 30 sec. The removal mechanism of the metallic contaminants like K, Fe and Cu in the remote plasma $H_2$ and the UV/$O_3$ cleaning processes is as follows: the metal atoms are lifted off by $SiO^*$ when the $SiO^*$is evaporated after the chemical $SiO_2$ formed under the metal atoms reacts with $H^+ \; and\; e^-$ to form $SiO^*$.

• Korean Journal of Materials Research
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• v.20 no.4
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• pp.210-216
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• 2010

This paper investigates the dependence of a-Si:H/c-Si passivation and heterojunction solar cell performances on various cleaning processes of silicon wafers. It is observed that the passivation quality of a-Si:H thin-films on c-Si wafers depends highly on the initial H-termination properties of the wafer surface. The effective minority carrier lifetime (MCLT) of highly H-terminated wafer is beneficial for obtaining high quality passivation of a-Si:H/c-Si. The wafers passivated by p(n)-doped a-Si:H layers have low MCLT regardless of the initial H-termination quality. On the other hand, the MCLT of wafers incorporating intrinsic (i) a-Si:H as a passivation layer shows sensitive variation with initial cleaning and H-termination schemes. By applying the improved cleaning processes, we can obtain an MCLT of $100{\mu}sec$ after H-termination and above $600{\mu}sec$ after i a-Si:H thin film deposition. By adapting improved cleaning processes and by improving passivation and doped layers, we can fabricate a-Si:H/c-Si heterojunction solar cells with an active area conversion efficiency of 18.42%, which cells have an open circuit voltage of 0.670V, short circuit current of $37.31\;mA/cm^2$ and fill factor of 0.7374. These cells show more than 20% pseudo efficiency measured by Suns-$V_{oc}$ with an elimination of series resistance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.04b
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• pp.31-34
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• 2000

It is very important to understand the correlation of between inter layer dielectric(ILD) CMP process and various facility factors supplied to equipment system. In this paper, the correlation between the various facility factors supplied to CMP equipment system and ILD CMP process were studied. To prevent the partial over-polishing(edge hot-spot) generated in the wafer edge area during polishing, we analyzed various facilities supplied at supply system. With facility shortage of D.I. water(DIW) pressure, we introduced an adding purified $N_2(PN_2)$ gas in polishing head cleaning station for increasing a cleaning effect. DIW pressure and PN2 gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. We estimated two factors (DIW pressure and PN2 gas) for the improvement of CMP process. Especially, we obtained a uniform planarity in patterned wafer and prohibited more than 90% wafer edge over-polishing. In this study, we acknowledged that facility factors supplied to equipment system played an important role in ILD-CMP process.