• 반도체디스플레이기술학회지
• /
• 제21권1호
• /
• pp.142-147
• /
• 2022

After introducing Hybrid Bonding technology into image sensors using stacked sensors and image processors, large quantity production became possible. As a result, it is currently used in most of the CMOS image market in smartphones and other image-based devices worldwide, and almost all stacked CIS manufacturing sites have focused on miniaturization using hybrid bonding. In this study, an upper wafer handling module for Wafer to Wafer Hybrid Bonding developed to increase the alignment and precision between wafers when wafer bonding. The module was divided two parts to reduce error of both the alignment and degree of precision during wafer bonding. Wafer handling module developed both new Tip/Tilt system controlling θx,θy of upper wafer and striker to push upper wafer. Based on this, it was confirmed through the stability evaluation that the upper wafer handling module can be controlled without any problem during W2W hybrid bonding.

• 한국정밀공학회지
• /
• 제16권3호통권96호
• /
• pp.78-83
• /
• 1999

The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

• 전기학회논문지
• /
• 제56권12호
• /
• pp.2217-2220
• /
• 2007

In this paper, we propose a new wafer level package (WLP) for the RF MEMS applications. The Film Bulk Acoustic Resonator (FBAR) are fabricated and hermetically packaged in a new wafer level packaging process. With the use of Au-Sn eutectic bonding method, we bonded glass cap and FBAR device wafer which has groove-shaped via formed in the backside. The device wafer includes a electrical bonding pad and groove-shaped via for connecting to the external bonding pad on the device wafer backside and a peripheral pad placed around the perimeter of the device for bonding the glass wafer and device wafer. The glass cap prevents the device from being exposed and ensures excellent mechanical and environmental protection. The frequency characteristics show that the change of bandwidth and frequency shift before and after bonding is less than 0.5 MHz. Two packaged devices, Tx and Rx filters, are attached to a printed circuit board, wire bonded, and encapsulated in plastic to form the duplexer. We have designed and built a low-cost, high performance, duplexer based on the FBARs and presented the results of performance and reliability test.

• 한국전기전자재료학회논문지
• /
• 제16권5호
• /
• pp.365-371
• /
• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• 반도체디스플레이기술학회지
• /
• 제16권1호
• /
• pp.29-33
• /
• 2017

This paper presents a development of vision aligner with three channels for the wafer and plate bonding machine in manufacturing of LED. The developed vision aligner consists of three cameras and performs wafer alignment of rotation and translation, flipped wafer detection, and UV Tape detection on the target wafer and plate. Normally the process step of wafer bonding is not defined by standards in semiconductor's manufacturing which steps are used depends on the wafer types so, a lot of processing steps has many unexpected problems by the workers and environment of manufacturing such as the above mentioned. For the mass production, the machine operation related to production time and worker's safety so the operation process should be operated at one time with considering of unexpected problem. The developed system solved the 4 kinds of unexpected problems and it will apply on the massproduction environment.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2005년도 추계학술대회 논문집
• /
• pp.427-431
• /
• 2005

In this study, 6' GaAs wafer bonding system is designed and optimized to bond 6 inches device wafer and material wafer. Bonding process is performed in vacuum environment and resin is used to bond two wafers. Vacuum module and double heating mechanisms are adopted to minimize wafer warpage and void. Structure and heat transfer analysis, et al of the core modules review the designed mechanisms are very effective in performance improvement. As a result, high productivity (tack time cut-down) and stabilized process can be obtained by reducing breakage failure of wafer.

• 반도체디스플레이기술학회지
• /
• 제20권4호
• /
• pp.171-176
• /
• 2021

Die-to-wafer (D2W) hybrid bonding in the multilayer semiconductor manufacturing process is one of wafer direct bonding, and various studies are being conducted around the world. A noteworthy point in the current die-to-wafer process is that a lot of voids occur on the bonding surface of the die during bonding. In this study, as a suggested method for removing voids generated during the D2W hybrid bonding process, a flexible mechanism for implementing convex for die bonding to be applied to the bond head is proposed. In addition, modeling of flexible mechanisms, analysis/design/control/evaluation of static/dynamics properties are performed. The proposed system was controlled by capacitive sensor (lion precision, CPL 290), piezo actuator (P-888,91), and dSpace. This flexure mechanism implemented a working range of 200 ㎛, resolution(3σ) of 7.276nm, Inposition(3σ) of 3.503nm, settling time(2%) of 500.133ms by applying a reverse bridge type mechanism and leaf spring guide, and at the same time realized a maximum step difference of 6 ㎛ between die edge and center. The results of this study are applied to the D2W hybrid bonding process and are expected to bring about an effect of increasing semiconductor yield through void removal. In addition, it is expected that it can be utilized as a system that meets the convex variable amount required for each device by adjusting the elongation amount of the piezo actuator coupled to the flexible mechanism in a precise unit.

• 한국재료학회지
• /
• 제8권10호
• /
• pp.890-897
• /
• 1998

n-InP(001)기판과 PECVD법으로 ${Si}_3N_4$(200nm)막이 성장된 InP 기판사이의 direct wafer bonding을 분석하였다. 두 기판을 접촉시켰을 때 이들 사이의 결합력에 크게 영향을 주는 표면 상태를 접촉각 측정과 AFM을 통해서 분석하였다. InP 기판은 $50{\%}$ 불산용액으로 에칭하였을 때 접촉각이 $5^{\circ}$, RMS roughness는 $1.54{\AA}$이었다. ${Si}_3N_4$는 암모니아수 용액으로 에칭하였을 때 RMS roughness가 $3.11{\AA}$이었다. Inp 기판과 ${Si}_3N_4$/InP를 각각 $50{\%}$ 불산 용액과 암모니아수 용액에 에칭한 후 접촉시켰을 때 상당한 크기의 초기 겹합력을 관찰할 수 있었다. 기계적으로 결합된 시편을 $580^{\circ}C$-$680^{\circ}C$, 1시간동안 수소 분위기와 질소분우기에서 열처리하였다. SAT(Scanning Acoustic Tomography)측정으로 두 기판 사이의 결합여부를 확인하였다. shear force로 측정한 InP 기판과 ${Si}_3N_4$/InP사이의 결합력은 ${Si}_3N_4$/InP 계면의 결합력만큼 증가되었다. TEM과 AES를 이용해서 di-rect water bonding 계면과 PECVD계면을 분석하였다.

• 마이크로전자및패키징학회지
• /
• 제19권2호
• /
• pp.29-33
• /
• 2012

The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

• 반도체디스플레이기술학회지
• /
• 제3권3호
• /
• pp.5-9
• /
• 2004

A new wafer level packaging scheme is presented as an alternative to MEMS package. The proof-of-concept structure is fabricated and evaluated to confirm the feasibility of the idea for MEMS wafer level packaging. The scheme of this work is developed using an electroplated tin (Sn) solder. The critical difference over conventional ones is that wafers are laterally bonded by solder reflow after LEGO-like assembly. This lateral bonding scheme has merits basically in morphological insensitivity and its better bonding strength over conventional ones and also enables not only the hermetic sealing but also its electrical interconnection solving an open-circuit problem by notching through via-hole. The bonding strength of the lateral bonding is over 30 Mpa as evaluated under shear and the hermeticity of the encapsulation is 2.0$\times10^{-9}$mbar.$l$/sec as examined by pressurized Helium leak rate. Results show that the new scheme is feasible and could be an alternative method for high yield wafer level packaging.