• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2002년도 추계학술대회 발표 논문집
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• pp.130-136
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• 2002

Device makers want to make higher density chips as devices shrink, especially WSix poly stack down is one of the key issues. However, EPD (End Point Detection) time delay was happened in DPS+ poly chamber which is a barrier to achieve device shrink because EPD time delay killed test pattern and next generation device. To investigate the EPD time delay, a test was done with patterned wafers. This experimental was carried out combined with OES(Optical Emission Spectroscopy) and SEM (Scanning Electron Microscopy). OES was used to find corrected wavelength in WSix stack down gate etching. SEM was used to confirm WSix gate profile and gate oxide damage. Through the experiment, a new wavelength (252nm) line of plasma is selected for DPS+ chamber to call correct EPD in WSix stack down gate etching for current device and next generation device.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.206-211
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• 2005

The device makers want to make higher density chips on the wafer through scale-down. The change of WSix/poly-Si gate film thickness is one of the key issues under 100 nm device structure. As a new device etching process is applied, end point detection(EPD) time delay was occurred in DPS+ poly chamber of Applied Materials. This is a barrier of device shrink because EPD time delay made physical damage on the surface of gate oxide. To investigate the EPD time delay, the experimental test combined with OES(Optical Emission Spectroscopy) and SEM(Scanning Electron Microscopy) was performed using patterned wafers. As a result, a EPD delay time is reduced by a new chamber seasoning and a new wavelength line through plasma scan. Applying a new wavelength of 252 nm makes it successful to call corrected EPD in WSix/poly-Si stack-down gate etching in the DPS+ poly chamber for the current and next generation devices.

• 전자공학회논문지
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• 제51권3호
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• pp.177-184
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• 2014

화학기상증착의 텅스텐 실리사이드 듀얼 폴리 게이트 구조에서 플로린이 게이트 산화막에 미치는 영향을 전기적 물리적 측정 방법을 사용하여 연구하였다. 플로린을 많이 함유한 텅스텐 실리사이드 NMOS 트랜지스터에서 채널길이가 감소함에 따라 게이트 산화막 두께는 감소하여 트랜지스터의 롤업(roll-off) 특성이 심화된다. 이는 게이트 재 산화막 열처리 공정에 의해 수직방향으로의 플로린 확산과 더불어 수평방향인 게이트 측면 산화막으로의 플로린 확산에 기인한다. 채널길이가 짧아질수록 플로린의 측면방향 확산거리가 작아져 수평방향 플로린 확산이 증가하고 그 결과 게이트 산화막의 두께는 감소하게 된다. 반면에 PMOS 트랜지스터에서는 P형 폴리를 만들기 위한 높은 농도의 붕소가 플로린의 게이트 산화막으로의 확산을 억제하여 채널길이에 따른 산화막 두께 변화 특성이 보이지 않는다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.481-482
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• 2008

In this paper, the advanced process has been presented to remove the WSix peeling that was made in sub 100nm DRAM SRCAT(Sphere-shaped-Recess-Ch annel-Array Transistor). The source of WSix peeling was proved to be the groove of gate poly film. We have completely solved the problems to adopt the gate-poly CMP (Chemical Mechanical Polishing) process.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.41-45
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• 2012

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

• 한국진공학회지
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• 제4권3호
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• pp.301-305
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• 1995

습식 분위기로 성장한 게이트 산화막 위에 다결정 실리콘(poly-Si)과 텅스텐 폴리사이드(WSix/poly-Si)게이트 전극을 형성하여 제작한 금속-산화물-반도체(metal-oxide-semiconductor:MOS)의 전기적 특성을 순간 절연파괴(time zero dielectric breakdown: TZDB)로 평가하였다. 텅스텐 폴리사이드 게이트 전극에 따른 게이트 산화막의 평균 파괴정계는 다결정 실리콘 전극보다 1.93MV/cm 정도 낮았다. 텅스텐 폴리사이드 게이트 전극에서 게이트 산화막의 B model(1-8 MV/cm)불량률은 dry O2 분위기에서 열처리함으로써 증가하였다. 이것은 열처리함으로써 게이트 전극이 silane(SiH4)에 의한 것보다 B mode 불량률이 감소하였다. 그것은 dichlorosilane 환원에 의한 텅스텐 실리사이드내의 불소 농도가 silane에 의한 것보다 낮기 때문이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.39-42
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• 2000

As gate dimensions continue to shrink below $0.2{\mu}m$, improving CD (Critical Dimension) control has become a major challenge during CMOS process development. Anti-Reflective Coatings are widely used to overcome high substrate reflectivity at Deep UV wavelengths by canceling out these reflections. In this study, we have investigated Batchtype system for PECVO SiOxNy as Anti-Reflective Coatings. The Singletype system was baseline and Batchtype system was new process. The test structure of Singletype is SiON $250{\AA}$ + Cap Oxide $50{\AA}$ and Batchtype is SiON $250{\AA}$ + Cap Oxide $50{\AA}$ or N2O plasma treatment. Inorganic chemical vapor deposition SiOxNy layer has been qualified for bottom ARC on Poly+WSix layer, But, this test was practiced on the actual device structure of TiN/Al-Cu/TiN/Ti stacks. A former day, in Batchtype chamber thin oxide thickness control was difficult. In this test, Batchtype system is consist of six deposition station, and demanded 6th station plasma treatment kits for N2O treatment or Cap Oxide after SiON $250{\AA}$. Good reflectivity can be obtained by Cap Oxide rather than N2O plasma treatment and both system of PECVD SiOxNy ARC have good electrical properties.