• The KIPS Transactions:PartC
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• v.15C no.4
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• pp.297-302
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• 2008

In case of display a lot of information from mobile devices, those systems are being developed that display the information from mobile devices on remote devices such as TV using the mobile devices as remote controllers because it is difficult to display a lot of information on mobile devices due to their limited bandwidth and small screen sizes. A lot of cost is required to design and develop interfaces for these systems corresponding to each of remote display devices. In this paper, a mobile environment based remote display system for displays at real times is proposed for continuous monitoring of status data for unique 'Mote IDs'. Also, remote data are collected and monitored through sensor network devices such as ZigbeX by applying status perception based remote displays at real times through processing ubiquitous computing environment data, and remote display applications at real times are implemented through PDA wireless mobiles. The system proposed in this paper consists of a PDA for remote display and control, mote embedded applications programming for data collections and radio frequency, server modules to analyze and process collected data and virtual prototyping for monitoring and controls by virtual machines. The result of the implementations indicates that this system not only provides a good mobility from a human oriented viewpoint and a good usability of accesses to information but also transmits data efficiently.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.7
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• pp.3140-3145
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• 2012

In this paper, a design method for a compact slot antenna fed by a coplanar waveguide (CPW) is studied. A T-shaped tuning stub is inserted inside a narrow rectangular slot and the slot is impedance matched to the CPW feedline by adjusting the width, length, and position of the stub. The resonance frequency is adjustable by the slot length and the antenna size can be reduced by bending the slot. The resonance frequency and impedance matching property of the compact slot antenna are similar to those of the half-wavelength slot antenna, which enables one to design compact antenna of this type with ease. A compact slot antenna for 2.45-GHz ISM band is designed, fabricated on an FR4 substrate (dielectric constant of 4.4 and thickness of 0.8 mm), and experimentally tested. The measured results agree well with the simulations, which confirms the validity of this study. The fabricated compact slot antenna shows an impedance bandwidth of 200 MHz(2.32-2.52 GHz) for a VSWR < 2, which is suitable for 2.45-GHz ISM band (2.4-2.48 GHz). The measured radiation patterns show ${\infty}$-shaped directional pattern in the E-plane and nearly omni-directional pattern in the H-plane with a peak gain of 2.0 dBi, which are similar to those of a monopole antenna. The proposed antenna is expected to be suitable for the applications as antennas for WLAN, RFID, and mobile handset.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.