• 한국건설관리학회논문집
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• 제2권4호
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• pp.48-61
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• 2001

본 연구에서는 작업 신뢰도 향상의 한 방안으로 기존 공정 관리 기법 상의 한계점을 분석하여 이를 보완하고자 하였다. 그 결과로써 린 생산 원리를 적용한 건설 생산 공정 개선 모델인 CPAM(Construction Process Analysis Model)을 제시하였다. CPAM의 변이 관리 기법을 통해 작업 변이를 최소화시켜 공정계획의 신뢰도 향상 및 생산 효율을 증대시킬 수 있도록 하였고 CPAM에서 제시된 세부작업 일정 계획과 주간작업계획을 통해 건설 현장의 작업 흐름에서 나타날 수 있는 자재, 장비, 인력등의 재고(Inventory or Work In Process, WIP)를 감소시킬 수 있도록 하였다. 또한 본 연구는 건설 생산을 작업 흐름의 관점으로 분석함으로써 기존의 분석에서 놓치기 쉬운 작업 흐름상에서의 불확실성을 최소화시키고 작업 처리량을 최대화시킬 수 있는 대안을 제시하는 데 그 의의가 있다.

• 한국시뮬레이션학회논문지
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• 제26권1호
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• pp.69-75
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• 2017

MCP(Multi-chip Package)는 두 개 이상의 Chip을 적층하여 하나의 패키지로 합친 제품이다. MCP를 만들기 위해서는 두 개 이상의 Chip이 동일한 Substrate에 적층되기 때문에 다수의 조립 공정이 필요하다. Package 공정에서는 Lot들이 동일한 특성을 가지는 Chip으로 구성되고 MCP를 구성하는 Chip의 특성은 Layer sequence에 의해 결정된다. MCP 생산 공정에서 WIP Balance 뿐만 아니라 Throughput을 달성하기 위해서는 Chip의 Layer sequence가 중요하다. 본 논문에서는 Chip들의 Layer sequence의 제약 조건을 고려한 스케쥴링 방법론을 제안한다.

• 전기학회논문지
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• 제57권4호
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• pp.692-699
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• 2008

Semiconductor research and development(R&D) fabs are very different than production fabs in many ways such as the scales of production, job priority, production methods, and performance measures. Efficient operations of R&D fabs are very important to the development of new product, process stability, high yield, and ultimately company competitiveness. This paper proposes the fab-wide scheduling method for operational optimization of the R&D fabs. Most scheduling systems of semiconductor fabs have only focused on maximizing throughput of each separated areas without considering WIP(works in process) flows of entire fab. In this paper, we proposes the a fab-wide scheduling system which schedules all lots to entire fab equipment at once. We develop the MIP(mixed integer programing) model which allocates the lots to production equipment considering many constraints of all processes and the CP(constraint programming) model which determines the sequences of the lots in the production equipment. The proposed FAB-wide scheduling model is applied to the newly constructed R&D fab. As a result, we have accomplished the system based automated job reservation, decrease of the hot lot delay, increase of the queue time satisfaction, the high throughput by maximizing the batch sizes, decrease of the WIP TAT(Turn Around Time).

• 경영과학
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• 제5권2호
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• pp.57-70
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• 1988

This paper examines both MRP and JIT for reducing WIP(Work In Process). The MRP/JIT system is suitable for multi-model, small-production manufacturing comparies in Korea because of the short delivery distance and low risk of accident during delivery. The objective of this paper is to manage vendors effectively by informing supply points and quantity of parts of vendors with MRP and JIT.

• 한국경영과학회:학술대회논문집
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• 한국경영과학회/대한산업공학회 2005년도 춘계공동학술대회 발표논문
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• pp.193-206
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• 2005

This paper considers a new flow-shop scheduling problem where a different WIP (work-in-process) state has different weight on the duration time. For the two machine case, the recognition version is NP-Complete in the strong sense. Several special cases are solved by different polynomial time algorithms. Finally, we develop a heuristic and provide an upper-bound on relative error which is tight in limit.

• 한국경영과학회:학술대회논문집
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• 한국경영과학회 2001년도 추계학술대회 논문집
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• pp.298-301
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• 2001

In semiconductor manufacturing, wafer fabrication is the most complicated and important process, which is composed of several hundreds of process steps and several hundreds of machines involved. The productivity of the manufacturing mainly depends on how well they control balance of WIP flow to achieve maximal throughput under short manufacturing cycle time. In this paper mathematical formulation is suggested for the stepper scheduling, in which cycle time reduction and maximal production is achieved.

• 산업공학
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• 제12권3호
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• pp.437-447
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• 1999

Modeling and system development for the fabrication process in the semiconductor manufacturing is presented in this paper. Maximization of wafer production can be achieved by the wafer flow balance under high utilization of bottleneck machines. Relatively simpler model is developed for the fabrication line by considering main characteristics of logistics. Simulation system is developed to evaluate the line performance such as balance rate, utilization, WIP amount and wafer production. Scheduling rules and input rules are suggested, and tested on the simulation system. We have shown that there exists good combination of scheduling and input rules.

• 경영과학
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• 제17권1호
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• pp.17-30
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• 2000

This paper addresses the effect of protective capacity on the lead time and throughput of a re-entrant line where statistical fluctuations exist in the form of variation in processing times and machine breakdowns. The specific framework employed in the paper is a five station re-entrant line structured as a closed network mode. This paper argues that protective capacity can be used in conjunction with WIP inventory in order to reduce the lead time and to increase the increase the throughput of a line. Simulation analyses are included to give insight into the effectiveness of protective capacity.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1711-1714
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• 2007

Various manufacturing methods are analyzed by using manufacturing metrics to validate which method would be applicable to flexible microelectronics. Among others, Roll-to-Roll method is revealed to inherently have an excessive WIP resulting in long cycle time and limited diversity as well as low equipment efficiency.

• 한국시뮬레이션학회:학술대회논문집
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• 한국시뮬레이션학회 2000년도 춘계학술대회 논문집
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• pp.131-136
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• 2000

FMS(Flexible Manufacturing System, 유연생산 시스템)는 1960년대 최초로 소개된 이후, 뛰어난 Throughput과 Flexibility로 지금까지 다양한 생산 현장에서 널리 활용되고 있다. 하지만 복잡한 Part의 흐름, 충분하지 못한 AGV(Automated Guided Vehicle) 등으로 인한 성능 저하는 가장 큰 장애물이라 할 수 있다. 이에 대한 대비책으로 시스템 내에 설치하는 버버는 일시적인 WIP(Work In Process, 재공재고)의 저장공간으로써 Blocking, Starving 등의 발생을 최소화하는 역할을 수행한다. 따라서 이러한 버퍼의 적절한 배치는 시스템 성능에 큰 영향을 미치게 되며, 이에 본 연구에서는 각 Workstation의 Workload를 고려해 각 버퍼의 적절한 Capacity를 결정하는 과정을 소개하며, 제시된 방법론의 실효성을 시뮬레이션을 통해 검증하고자 한다.