• Korean Journal of Construction Engineering and Management
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• v.2 no.4 s.8
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• pp.48-61
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• 2001

This study aims at improving work reliability. It proposes a way to overcome the limitations of current scheduling methods by providing a new framework, CPAM(Construction Process Analysis Model) based on the lean principles. It suggests methods which improve work reliability and production effectiveness with variability control methods. Also it suggests methods which reduce inventories of materials and equipment and WIP(Work In Process) using two techniques; Lookahead Schedule and Weekly Work Plan. The contribution of this research also includes that it assumes planning as a process of reducing uncertainty and maximizing throughput, counter-posing plan reliability to resource redundancy as alternative strategies for managing in conditions of uncertain work flow.

• Journal of the Korea Society for Simulation
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• v.26 no.1
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• pp.69-75
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• 2017

An MCP(Multi-chip Package) is a package consisting of several chips. Since several chips are stacked on the same substrate, multiple assembly steps are required to make an MCP. The characteristics of the chips in the MCP are dependent on the layer sequence. In the MCP manufacturing process, it is very essential to carefully consider the layer sequence in scheduling to achieve the intended throughput as well as the WIP balance. In this paper, we propose a scheduling methodology considering the layer sequence constraint.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.692-699
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• 2008

Semiconductor research and development(R&D) fabs are very different than production fabs in many ways such as the scales of production, job priority, production methods, and performance measures. Efficient operations of R&D fabs are very important to the development of new product, process stability, high yield, and ultimately company competitiveness. This paper proposes the fab-wide scheduling method for operational optimization of the R&D fabs. Most scheduling systems of semiconductor fabs have only focused on maximizing throughput of each separated areas without considering WIP(works in process) flows of entire fab. In this paper, we proposes the a fab-wide scheduling system which schedules all lots to entire fab equipment at once. We develop the MIP(mixed integer programing) model which allocates the lots to production equipment considering many constraints of all processes and the CP(constraint programming) model which determines the sequences of the lots in the production equipment. The proposed FAB-wide scheduling model is applied to the newly constructed R&D fab. As a result, we have accomplished the system based automated job reservation, decrease of the hot lot delay, increase of the queue time satisfaction, the high throughput by maximizing the batch sizes, decrease of the WIP TAT(Turn Around Time).

• Korean Management Science Review
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• v.5 no.2
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• pp.57-70
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• 1988

This paper examines both MRP and JIT for reducing WIP(Work In Process). The MRP/JIT system is suitable for multi-model, small-production manufacturing comparies in Korea because of the short delivery distance and low risk of accident during delivery. The objective of this paper is to manage vendors effectively by informing supply points and quantity of parts of vendors with MRP and JIT.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2005.05a
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• pp.193-206
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• 2005

This paper considers a new flow-shop scheduling problem where a different WIP (work-in-process) state has different weight on the duration time. For the two machine case, the recognition version is NP-Complete in the strong sense. Several special cases are solved by different polynomial time algorithms. Finally, we develop a heuristic and provide an upper-bound on relative error which is tight in limit.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2001.10a
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• pp.298-301
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• 2001

In semiconductor manufacturing, wafer fabrication is the most complicated and important process, which is composed of several hundreds of process steps and several hundreds of machines involved. The productivity of the manufacturing mainly depends on how well they control balance of WIP flow to achieve maximal throughput under short manufacturing cycle time. In this paper mathematical formulation is suggested for the stepper scheduling, in which cycle time reduction and maximal production is achieved.

• IE interfaces
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• v.12 no.3
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• pp.437-447
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• 1999

Modeling and system development for the fabrication process in the semiconductor manufacturing is presented in this paper. Maximization of wafer production can be achieved by the wafer flow balance under high utilization of bottleneck machines. Relatively simpler model is developed for the fabrication line by considering main characteristics of logistics. Simulation system is developed to evaluate the line performance such as balance rate, utilization, WIP amount and wafer production. Scheduling rules and input rules are suggested, and tested on the simulation system. We have shown that there exists good combination of scheduling and input rules.

• Korean Management Science Review
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• v.17 no.1
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• pp.17-30
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• 2000

This paper addresses the effect of protective capacity on the lead time and throughput of a re-entrant line where statistical fluctuations exist in the form of variation in processing times and machine breakdowns. The specific framework employed in the paper is a five station re-entrant line structured as a closed network mode. This paper argues that protective capacity can be used in conjunction with WIP inventory in order to reduce the lead time and to increase the increase the throughput of a line. Simulation analyses are included to give insight into the effectiveness of protective capacity.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1711-1714
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• 2007

Various manufacturing methods are analyzed by using manufacturing metrics to validate which method would be applicable to flexible microelectronics. Among others, Roll-to-Roll method is revealed to inherently have an excessive WIP resulting in long cycle time and limited diversity as well as low equipment efficiency.

• Proceedings of the Korea Society for Simulation Conference
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• 2000.04a
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• pp.131-136
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• 2000

FMS(Flexible Manufacturing System, 유연생산 시스템)는 1960년대 최초로 소개된 이후, 뛰어난 Throughput과 Flexibility로 지금까지 다양한 생산 현장에서 널리 활용되고 있다. 하지만 복잡한 Part의 흐름, 충분하지 못한 AGV(Automated Guided Vehicle) 등으로 인한 성능 저하는 가장 큰 장애물이라 할 수 있다. 이에 대한 대비책으로 시스템 내에 설치하는 버버는 일시적인 WIP(Work In Process, 재공재고)의 저장공간으로써 Blocking, Starving 등의 발생을 최소화하는 역할을 수행한다. 따라서 이러한 버퍼의 적절한 배치는 시스템 성능에 큰 영향을 미치게 되며, 이에 본 연구에서는 각 Workstation의 Workload를 고려해 각 버퍼의 적절한 Capacity를 결정하는 과정을 소개하며, 제시된 방법론의 실효성을 시뮬레이션을 통해 검증하고자 한다.