• Journal of the Semiconductor & Display Technology
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• v.15 no.4
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• pp.79-85
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• 2016

For long life time and high efficiency, not necessary in improvement of LED chip structure, but also improve heat radiation for decrease heat in LED chip. In this study, efficiency decline factor has been investigated in LED lamp as study heat characteristic, luminance flux and heat resistance. When LED lamp temperature was increased, about 7% loss of luminance flux. In consequence of temperature analysis, width of fin was the most important factor of heat radiation. As a result, secure the enough heat path is very important factor of LED lamp design.

• Proceedings of the KSME Conference
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• 2007.05b
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• pp.2449-2452
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• 2007

Hot spots on thin wafers of IC packages are becoming important issues in thermal and electrical engineering fields. To investigate these hot spots, we developed a Diode Temperature Sensor Array (DTSA) that consists of an array of 32 ${\times}$32 diodes (1,024 diodes) in a 8 mm ${\times}$ 8 mm surface area. To know specifically the hot spot temperature which is affected by the chip thickness and a generated power, we made the DTSA chips, which have 21.5 ${\mu}m$, 31 ${\mu}m$, 42 ${\mu}m$, 100 ${\mu}m$, 200 ${\mu}m$, and 400 ${\mu}m$ thickness using the CMP process. And we conducted the experiment using various heater power conditions (0.2 W, 0.3 W, 0.4 W, 0.5 W). In order to validate experimental results, we performed a numerical simulation. Errors between experimental results and numerical data are less than 4%. Finally, we proposed a correlation for the hot spot temperature as a function of the generated power and the wafer thickness based on the results of the experiment. This correlation can give an easy estimate of the hot spot temperature for flip chip packaging when the wafer thickness and the generated power are given.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.3
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• pp.234-239
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• 2007

This paper describes the TiW ohmic contact characteristics under the surface treatment of the polycrystalline 3C-SiC thin film grown on $SiO_2/Si(100)$ wafers by APCVD. The poly 3C-SiC surface was polished by using CMP(chemical mechanical polishing) process and then oxidized by wet-oxidation process, and finally removed SiC oxide layers. A TiW thin film as a metalization process was deposited on the surface treated poly 3C-SiC layer and was annealed through a RTA(rapid thermal annealing) process. TiW/poly 3C-SiC was investigated to get mechanical, physical, and electrical characteristics using SEM, XRD, XPS, AFM, optical microscope, I-V characteristic, and four-point probe, respectively. Contact resistivity of the surface treated 3C-SiC was measured as the lowest $1.2{\times}10^{-5}{\Omega}cm^2$ at $900^{\circ}C$ for 45 sec. Therefore, the surface treatments of poly 3C-SiC are necessary to get better contact resistance for extreme environment MEMS applications.

• Journal of Pharmaceutical Investigation
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• v.20 no.2
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• pp.89-95
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• 1990

Ethylcellulose-PEG 4000 film coated on core tablets was investigated as a potential drug delivery system for the controlled release of chlorpheniramine maleate (CPM). The kinetic analysis of the release data indicated that CPM release followed a diffusion-controlled model, where the quantity released per unit area is proportional to the square root of time. The effect of the film composition, CPM concentration, plasticizer concentration and CPM solubility on the release characteristics were examined. The release rate constant increased as CPM concentration increased. It also increased as the PEG 4000 content in the film increased above 10%(w/w), however, it decreased as the PEG 4000 content increased in the concentration range below 10%(w/w). The release rate constant was not affected by the coated weight on the core tablet. The film-coated tablets which contain CPM only in the coated film layer seemed to be a potential oral drug delivery system for the controlled release of CPM.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.61-66
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• 2012

Chemical Mechanical Planarization (CMP) is a polishing process used in the microelectronic fabrication industries to achieve a globally planar wafer surface for the manufacturing of integrated circuits. Pad conditioning plays an important role in the CMP process to maintain a material removal rate (MRR) and its uniformity. For metal CMP process, highly acidic slurry containing strong oxidizer is being used. It would affect the conditioner surface which normally made of metal such as Nickel and its alloy. If conditioner surface is corroded, diamonds on the conditioner surface would be fallen out from the surface. Because of this phenomenon, not only life time of conditioners is decreased, but also more scratches are generated. To protect the conditioners from corrosion, thin organic film deposition on the metal surface is suggested without requiring current conditioner manufacturing process. To prepare the anti-corrosion film on metal conditioner surface, vapor SAM (self-assembled monolayer) and FC (Fluorocarbon) -CVD (SRN-504, Sorona, Korea) films were prepared on both nickel and nickel alloy surfaces. Vapor SAM method was used for SAM deposition using both Dodecanethiol (DT) and Perfluoroctyltrichloro silane (FOTS). FC films were prepared in different thickness of 10 nm, 50 nm and 100 nm on conditioner surfaces. Electrochemical analysis such as potentiodynamic polarization and impedance, and contact angle measurements were carried out to evaluate the coating characteristics. Impedance data was analyzed by an electrical equivalent circuit model. The observed contact angle is higher than 90o after thin film deposition, which confirms that the coatings deposited on the surfaces are densely packed. The results of potentiodynamic polarization and the impedance show that modified surfaces have better performance than bare metal surfaces which could be applied to increase the life time and reliability of conditioner during W CMP.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.369-373
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• 2012

최근 강화된 국내외의 배출가스 규제 조건을 충족시키기 위해, 사용자의 요구대로 연료의 분사시기와 분사량을 조절할 수 있는 CRDI ECU 제어 알고리즘의 개발이 필요하다. 따라서 본 논문에서는 산업용 CRDI 엔진 전용 ECU에 적용할 수 있는 노킹 판별 및 엔진 밸런스 보정이 가능한 노킹 분석 시뮬레이터를 개발하였다. 개발한 노킹 분석 시뮬레이터의 결과를 OBD-II 표준을 사용하여 차량 위주의 진단기를 개발하여 운전자가 직접 차량을 진단할 수 있는 운전자 중심의 진단 서비스를 제공하고자 한다. 이를 위해 자동차 고장진단 신호 및 센서 출력 신호를 유선시스템과 무선 시스템인 블루투스 모듈을 이용하여 실시간 통신이 제공 될 수 있는 OBD-II 진단기 S/W 설계 방안을 제안함으로써 차량의 연비를 향상시키고, 유해 배출가스의 발생을 최소화하여 엔진 효율성의 개선 방안을 제시하고자 한다.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.130-137
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• 1995

Deopsition of thermal quality SiO2 using a high density plasma ECR CVD process has been demonstrated to give void and seam free gap fill of high aspect ratio metallization structures with a simple oxygen-silane chemistry. This is achieved by continuous sputter etching of the film during the deposition process. A two-step process is utilized to deposit a composite layer for higher manufacturing efficiency. The first step, which has a deposition rate of approximately 0.5 $\mu$m/min., is used to provide complete gap fill between the metal lines. The second step, which has a deposition rate of up to 1.5 $\mu$m/min., is used to deposit a total thickness of 2.0$\mu$m for the intermetal dielectric film. The topography of this composite film is very compatible with subsequent chemicl mechanical polishing(CMP) planarization processing.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.402-409
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• 2013

An innovative application of voltage-contrast (VC) inspection allowed inline detection of NMOS leakage in dense SRAM cells is presented. Cell sizes of SRAM are continual to do the shrinkage with bit density promotion as semiconductor technology advanced, but the resulting challenges include not only development of smaller-scale devices, but also intra-devices isolation. The NMOS leakage caused by the underneath n+/P-well shorted to the adjacent PMOS/N-well was inspected by the proposed electron-beam (e-beam) scan in which VC images were compared during the in-line process step of post contact tungsten (W) CMP (Chemical Mechanical Planarization) instead of end-of-line electrical test, which has a long response time. A series of experiments based on the mechanism for improving the intra-well isolation was performed and verified by the inline VC inspection. An optimal process-integration condition involved to the tradeoff between the implant dosage and photo CD was carried out.

• Journal of Life Science
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• v.25 no.2
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• pp.197-205
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• 2015

The comparative effects of the fibrinolytic action, antioxidative activity, and tyrosinase inhibition of Cordyceps militaris powder and fermented Cordyceps militaris powders were investigated using several microscopic organisms. The nutritional components such as phenolic compounds, flavonoids, and minerals were also measured. The total phenolic compounds and flavonoid concentrations were highest in the Cordyceps militaris powder fermented by Aspergillus oryzae. Major minerals were K, Ca, Mg, and Zn. Native polyacrylamide gel electrophoresis (native-PAGE) analysis of the total protein patterns of Cordyceps militaris powder and fermented Cordyceps militaris powders revealed slight varietal differences. Fibrinolytic activity was highest in the Cordyceps militaris powder fermented by Bacillus subtilis and Aspergillus kawachii. The DPPH radical scavenging activity was slightly stronger in the powder fermented by Monascus purpureus; however, these samples all exhibited a relatively low activity when compared with butylated hydroxytoluene (BHT). Tyrosinase inhibition activity was stronger in the powder fermented by Aspergillus oryzae than in unfermented powder. These results may provide basic data for understanding the biological activities and chemical characteristics of Cordyceps militaris powder fermented by several microscopic organisms for the development of functional foods.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.