• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.3
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• pp.293-301
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• 2011

This paper proposes a bridgeless half-bridge AC-DC converter with high-efficiency. The proposed converter integrates the bridgeless power factor correction (PFC) circuit with the asymmetrical pulse-width modulated (APWM) half-bridge DC-DC converter. It provides the isolated DC output voltage from the AC line voltage without using any full-bridge diode rectifier. Conduction losses are lowered with a simple circuit structure. Switching losses are also reduced by achieving zero-voltage switching (ZVS) of the power switches. By using series-connected two transformers, the proposed converter provides a low-profile and high power density for AC-DC converters. The performance of the proposed converter is verified from a 250 W (48 V / 5.2 A) experimental prototype circuit at $90 \;V_{rms}$ line voltage.

• Journal of the Korean Society for Railway
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• v.15 no.4
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• pp.357-363
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• 2012

This paper presents a new operation method for the single phase PWM(Pulse Width Modulation) converter train. Recently, the trains adopting the PWM converter have become the majority in the electric locomotives since there are distinct advantages over the predecessors, which can be operated at near unity power factor. However, a slight modification of the control scheme makes this kind of vehicles run in the region of leading power factor. Although this feature seems to be of no significant use by itself, the leading phase operation can improve the voltage profile and the line loss of the feeding systems is decreased by compensating the reactive power loss along the line when it considered together with the feeding systems. This method is even more economical and efficient comparing with the installation of SVC that is mainly used for this purpose since the train can become a movable compensator. With the conditions and some essential formula for the leading phase operation, a new power factor control algorithm has been proposed to implement this scheme. The results of simulation through SIMULINK model show that the proposed method is suitable enough for practical use.

• Bulletin of the Korean Chemical Society
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• v.25 no.4
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• pp.511-516
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• 2004

A Li$[Co_{0.17}Li_{0.28}Mn_{0.55}]O_2$ cathode compound was prepared by a simple combustion method. The X-ray diffraction pattern showed that this compound could be classified as ${\alpha} -NaFeO_2$ structure type with the lattice constants of a = 2.8405(9) ${\AA}$ and c = 14.228(4) ${\AA}$. According to XANES analysis, the oxidation state of Mn and Co ions in the compound were 4+ and 3+, respectively. During the first charge process, the irreversible voltage plateau at around 4.65 V was observed. The similar voltage-plateau was observed in the initial charge profile of other solid solution series between $Li_2MnO_3\;and\;LiMnO_2$ (M=Ni, Cr...). The first discharge capacity was 187 mAh/g and the second discharge capacity increased to 204 mAh/g. As the increase of cycling number, one smooth discharge profile was converted to two distinct sub-plateaus and the discharge capacity was slowly decreased. From the Co and Mn K-edge XANES spectra measured at different cyclic process, it can be concluded that irreversible transformation of phase is occurred during continuous cycling process.

• Korean Journal of Materials Research
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• v.20 no.8
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• pp.434-438
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• 2010

The selenization process has been a promising method for low-cost and large-scale production of high quality CIGS film. However, there is the problem that most Ga in the CIGS film segregates near the Mo back contact. So the solar cell behaves like a $CuInSe_2$ and lacks the increased open-circuit voltage. In this study we investigated the Ga distribution in CIGS films by using the $Ga_2Se_3$ layer. The $Ga_2Se_3$ layer was applied on the Cu-In-Ga metal layer to increase Ga content at the surface of CIGS films and to restrict Ga diffusion to the CIGS/Mo interface with Ga and Se bonding. The layer made by thermal evaporation was showed to an amorphous $Ga_2Se_3$ layer in the result of AES depth profile, XPS and XRD measurement. As the thickness of $Ga_2Se_3$ layer increased, a small-grained CIGS film was developed and phase seperation was showed using SEM and XRD respectively. Ga distributions in CIGS films were investigated by means of AES depth profile. As a result, the [Ga]/[In+Ga] ratio was 0.2 at the surface and 0.5 near the CIGS/Mo interface when the $Ga_2Se_3$ thickness was 220 nm, suggesting that the $Ga_2Se_3$ layer on the top of metal layer is one of the possible methods for Ga redistribution and open circuit voltage increase.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.32 no.4
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• pp.297-302
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• 2008

We present an electrical particle velocity profiler using particle transit time across uneven inter-gap electrodes. We measure both the particle position and velocity from the voltage signals generated by the particles passing across sensing electrodes, thus obtaining the velocity profile of the particles in a microfluidic channel. In the experimental study, we use polystyrene microparticles to characterize the performance of the electrical particle velocity profiler. The particle velocity profile is measured with the uncertainty of 5.44%, which is equivalent to the uncertainty of 5% in the previous optical method. We also experimentally demonstrate the capability of the present method for in-channel clogging detection. Compared to the previous optical methods, the present electrical particle velocity profiler offers the simpler structure, the cheaper cost, and the higher integrability to micro-biofluidic systems.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.223-226
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• 2003

We propose an improvement method for a $\underline{G}ate$ $\underline{OX}ide(GOX)$ thinning at the edge of $\underline{S}hallow$ $\underline{T}rench$ $\underline{I}solation(STI)$, when STI is adopted to Dual Gate Oxide(DGOX) Process. In the case of SOC(System On-a-Chip), the DGOX process is usually used for realizing both a low and a high voltage parts in one chip. However, it is found that the severe GOX thinning occurs from at STI top edge region and a dent profile exists at the top edge of STI, when conventional DGOX and STI process carried out in high density device chip. In order to overcome this problem, a new DGOX process is tried in this study. And we are able to prevent the GOX thinning by H2 anneal, partially SiN liner skip, and a method which is merged a thick sidewall oxide(S/O) with a SiN pull-back process. Therefore, a good subthreshold characteristics without a double hump is obtained by the prevention of a GOX thinning and a deep dent profile.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.213-216
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• 2001

Etching behaviors of ferroelectric YMn $O_3$ thin films were studied by an inductively coupled plasma (ICP). Etch characteristic on ferroelectric YMn $O_3$ thin film have been investigated in terms of etch rate, selectivity and etch profile. The maximum etch rate of YMn $O_3$ thin film is 300 $\AA$/min at Ar/C $l_2$ of 2/8, RF power of 800W, dc bias voltage of 200V, chamber pressure of 15mTorr and substrate temperature of 3$0^{\circ}C$. Addition of C $F_4$ gas decrease the etch rate of YMn $O_3$ thin film. From the results of XPS analysis, Y $F_{X}$ compunds were found on the surface of YMn $O_3$ thin film which is etched in Ar/C1/C $F_4$ plasma. The etch profile of YMn $O_3$ film is improved by addition of C $F_4$ gas into the Ar/C $l_2$ plasma. These results suggest that fluoride yttrium acts as a sidewall passivants which reduce the sticking coefficient of chlorine on YMn $O_3$.>.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.539-542
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• 2003

Recently, the polymer insulators which are being used for high voltage applications have some advantages such as light weight, small size, vandalism resistance, hydrophobicity and easy making process. During outdoor service of polymer insulators, the surface of the insulating material is frequently subjected to moisture and contamination which lead to the well known phenomenon of dry band arcing. Their tracking resistance, erosion resistance, end sealing and shed design are very important because dry band arcing causes degradation of polymer surface. The shape design of porcelain insulator is formalized but design standard for polymer insulator is no standardized up to now, much research is necessary in real condition. In this paper, the aging property of polymer insulator with shed shape(regular, alternative type) is analyzed through numerical analysis, CEA(canadian electricity association) tracking wheel test and IEC 61109 Annex C.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.6
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• pp.535-540
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• 2022

DC-link capacitors are reliability-critical components in a photovoltaic (PV) inverter. Typically, the lifetime of a DC-link capacitor is evaluated by considering the voltage and hot-spot temperature of the capacitor under the specific operating condition of the PV inverter. However, the output of the PV inverter is determined by solar irradiation and ambient temperature, which vary with the seasons; accordingly, the hot-spot temperature of the capacitor also changes. Therefore, the mission profile of the PV system should be considered to effectively evaluate the reliability of the DC-link capacitor. In this study, the reliability of the DC-link capacitor of a three-level NPC inverter is comparatively analyzed with and without considering the mission profiles of the PV system, where two mission profiles recorded in Arizona and Iza are considered. The accumulated damage of the DC-link capacitor is calculated based on the lifetime model by analyzing its thermal loading. Afterward, a reliability evaluation of the DC-link capacitor is performed at the component level and then at the system level by considering all capacitors by means of Monte Carlo analysis. Results reveal the importance of performing a mission-profile-based reliability evaluation during the design of high-reliability PV inverters to achieve the target reliability performance.

• Journal of Energy Engineering
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• v.12 no.1
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• pp.42-48
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• 2003

In system planing and operation, voltage and reactive power control is very important. The voltage deviation and system losses can be reduced through control of reactive power sources. In general, there are several different reactive power sources, we used switched shunt capacitor to improve the voltage profile and to reduce system losses. Since there are many switched shunt capacitors in power system, so it if necessary to coordinate these switched shunt capacitors. In this study, Genetic Algorithm (GA) is used to find optimal coordination of switched shunt capacitors in a local area of power system. In case study, the effectiveness of the proposed method is demonstrated in KEPCO's power system. The simulation is performed by PSS/E and the results of simulation are compared with sensitivity method.