• 전기학회논문지
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• 제57권11호
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• pp.1976-1980
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• 2008

This paper deals the characteristic analysis of Switched Reluctance Motor(SRM) driven by single-pulse mode considering dc link voltage ripple. Two dimensional time-stepped Finite Element Method(FEM) is used to analyze the characteristic of SRM driven by single-pulse mode with dc link voltage ripple. The analysis results is verified by experimental test.

• Journal of Electrical Engineering and Technology
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• 제10권1호
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• pp.195-204
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• 2015

In this paper, the development of a cost-effective active power filter/uninterruptible power supply (APF/UPS) system with seamless mode transfer is described. The proposed scheme employs a pulse-width-modulation (PWM) voltage-source inverter and has two operational modes. First, when the source voltage is normal, the system operates as an APF, which compensates for the harmonics and power factor while boosting the DC-link voltage to be ready for the disturbance, without an additional DC charging circuit. A simple algorithm to detect the load current harmonics is also proposed. Second, when the source voltage is out of the normal range (owing to sag, swell, or outage), it operates a UPS, which controls the output voltage constantly by discharging the DC-link capacitor. Furthermore, a seamless transfer method for the single-phase inverter between the APF mode and the UPS mode is also proposed, in which an IGBT switch with diodes is used as a static bypass switch. Dissimilar to a conventional SCR switch, the IGBT switch can implement a seamless mode transfer. During the UPS operation, when the source voltage returns to the normal range, the system operates as an APF. The proposed system has good transient and steady-state response characteristics. The APF, charging circuit, and UPS systems are implemented in one inverter system. Finally, the validity of the proposed scheme is investigated with simulated and experimental results for a prototype APF/UPS system rated at 3 kVA.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.399-400
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• 2012

The proposed battery charger presented in this paper is suitable for Lead-Acid Battery and the dc/dc buck converter topology is applied as a charger circuit. The technique adopted in this charger is constant current & constant voltage dual mode, which is decided by the value of voltage of proposed battery. Automatic mode change function is detected by the percentage value of level of battery charging. CC Mode (Constant Current Mode) is operated when charging level is below 80% of the total charging of Battery voltage and above 80% of battery voltage charging, CV Mode (Constant Voltage Mode) is automatically operated. As the charging level exceeds 120%, it automatically terminates charging. The feedback signal to the PWM generator for charging the battery is controlled by using the current and voltage measurement circuits simultaneously. This technique will degrade the damage of proposed type of battery and improve the power efficiency of charger. Finally, a prototype charger circuit designed for a 12-V 7-Ah lead acid battery is constructed and tested to confirm the theoretical predictions. Satisfactory performance is obtained from simulation and the experimental results.

• Journal of Power Electronics
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• 제19권1호
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• pp.108-118
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• 2019

This paper proposes a DC-link voltage balance controller using the fourth-phase of a three-level neutral-point clamped (NPC) PWM converter with medium vector selection (MVS) PWM for common-mode voltage reduction. MVS PWM makes the voltage reference by synthesizing the voltage vectors that cannot generate common-mode voltage. This PWM method is effective for reducing the EMI noise emitted from converter systems. However, the DC-link voltage imbalance problem is caused by the use of limited voltage vectors. Therefore, in this paper, the effect of MVS PWM on the DC-link voltage of a three-level NPC converter is analyzed. Then a proportional-derivative (PD) controller for the DC-link voltage balance is designed from the DC-link modeling. In addition, feedforward compensation of the neutral point current is included in the proposed PD controller. The effectiveness of the proposed controller is verified by experimental results.

• 전력전자학회논문지
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• 제21권1호
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• pp.27-33
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• 2016

A pulse-width modulation (PWM) method for common mode noise reduction in a PWM inverter connected to a single-phase grid is proposed in this study. The extensively used conventional switching method may experience common mode voltage problems, which generate current leakage and electromagnetic induction problems. In the proposed switching method, the neutral point of the output voltage is always fixed at both ends of the input voltage to reduce common mode noise. The validity of the proposed method is proven through simulation and experimental results.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 B
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• pp.1232-1234
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• 2004

In this paper, we represent both occurrence reason of Surge-voltage and Leakage current of AC drive system which is operated by Voltage-type PWM Inverter. It generates a compensating voltage which has the same amplitude as, but the opposite phase to, the common-mode voltage produced by the PWM inverter. The compensating voltage is superimposed on the inverter output by a common-mode transformer. As a result, the common-mode voltage applied to the load is canceled completely. The design method of the active common-mode noise canceler is also presented in detail. Therefore, we try to describe the method controling both of them and all of the proprieties are proved by our experiment.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 D
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• pp.1156-1158
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• 1997

This paper presents the proposed full-order observer-based sliding mode power system stabilizer(FOOSMPSS) for finding unmeasurable state variables(torque angle, quadratic-axis transient voltage, exciter output voltage, voltage regulator output voltage and output voltage) by measuring angular velocity. The simulation results is shown by the comparison of the FOOPSS with the proposed FOOSMPSS.

• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1645-1655
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• 2016

A Dynamic Voltage Restorer (DVR) model is proposed to eliminate the short-term voltage disturbances that occur in the grid-connected mode, the switching between grid-connected mode and the stand-alone mode of a Microgrid. The proposed DVR structure is based on a conventional cascaded H-bridge multilevel inverter (MLI) topology; a novel composite control strategy is presented, which could ensure the compensation ability of voltage sag by the DVR. Moreover, the compensation to specified order of harmonic is added to implement effects that zero-steady error compensation to harmonic voltage in specified order of the presented control strategy; utilizing wind turbines-batteries units as DC energy storage components in the Microgrid, the operation cost of the DVR is reduced. When the Microgrid operates under stand-alone mode, the DVR can operate on microsource mode, which could ease the power supply from the main grid (distribution network) and consequently be favorable for energy saving and emission reduction. Simulation results validate the robustness and effective of the proposed DVR system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 B
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• pp.1515-1517
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• 2005

In this paper, we represent both occurrence reason of Surge-voltage and Leakage-current of AC drive system which is operated by Voltage-type PWM Inverter. It generates a compensating voltage which has the same amplitude as, but the opposite phase to, the common-mode voltage produced by the PWM inverter. The compensating voltage is superimposed on the inverter output by a common-mode transformer. As a result, the common-mode voltage applied to the load is canceled completely. The design method of the active common-mode noise canceler is also presented in detail. Therefore, we try to describe the method controling both of them and all of the proprieties are proved by our experiment.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.423-429
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• 2013

A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.