• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1030-1033
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• 2002

This paper, a new simple controller operates in continuous conduction mode (CCM) for Boost power factor collection converter is introduced. The duty ratios are obtained by comparisons of a sensed signal from inductor current and a negative ramp carrier waveform in each switching period. By using the proposed controller, input voltage sensing, error amplifier in the current feedback loop, and analog multiplier／divider are not required, then, the control circuit implementation is very simple. To verify the proposed controller, the circuit simulation for Boost power factor correction converter was applied. For the results, the input current waveform was shaped to be closely sinusoidal, implying low THD.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.505-508
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• 1999

Conventional adaptive speed estimators cannot avoid the influence of the non-linear inductance variation under the saturation conditions. Without speed sensors, it is difficult to identify the inductance variation using a reactive power mode because the model contains a term of the rotor speed. In this paper, we propose a novel speed estimator having hybrid architecture in order to estimate both the rotor speed and the inductance variation simultaneously when the motor flux is saturated. Proposed estimator consists of the error between the flux obtained from the stator voltage equation and the flux estimated from the rotor flux observer. Introducing a new correction term into the estimator increases the estimation ability of the conventional speed estimator even though the motor flux is saturated. The convergence of the speed estimation error is examined by simulation Furthermore, the experimental results show the validity of the proposed method.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.403-406
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• 1998

There are two cases of error occurrence of STT(Smart Temperature Transmitter). One is that because of unstable reference voltage, data from A/D converter is not reliable. The other is that because of change of room temperature, this change affects conversion of A/D converter. In this paper, we show algorithms be adapted to STT for reliable conversion of A/D converter through a experiment and compensation for temperature change. In a experiment, we collect data from reference voltage and ground then calculate nominal value of these at constant temperature during A/D converter initialization or at any conversion time. Algorithm for compensation for unstable reference voltage calculates a correction factor and adapts it to compensation for malfunction of A/D converter. Algorithm for compensation for variation of room temperature is come from linearization of thermistor but is adapted to zener diode, not thermistor, therefor we have less effort for compensation for temperature and have a idea that it can be adapted to A/D converter system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Proceedings of the KIEE Conference
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• 1997.07e
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• pp.1684-1687
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• 1997

In this paper, a three-dimensional algorithm for the insulation design of the high-voltage equipment is presented. In general, the insulation design consists of two steps. They are electric field calculation and correction of the shape to be designed. In the proposed algorithm, the combination method of charge simulation and surface charge simulation is used to calculate the three-dimensional electric fields. As for the correction of the shape, indirect control provided by rational B-spline is more useful than direct control. The use of rational B-spline reduces in the number of design variables and garrantees the smooth curvature of the designed shape. The proposed algorithm is applied to the design of the shape of the shield ring which has been designed by the method of trial and error.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.9
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• pp.1275-1282
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• 2012

This paper proposes the 16-channel LED Driver IC for Full color LED display system. The proposed LED driver IC in this paper can draw current independent of temperature and supply voltage in each channel. Current flow in the channel is configurable via an external resistor. LED brightness is adjusted by 12-Bit PWM(Pulse Width Modulation) and 8-Bit DC(Dot Correction). A real-time monitoring of IC temperature ($130^{\circ}C/150^{\circ}C$) and LED status (open/short) is provided by LED driver IC and the user can receive warning and get information on problems. A 16-channel LED driver IC is produced using 0.35 um BCD process and the size is $2.5mm{\times}2.5mm$. In this paper, channel current characteristic and channel current control function were measured in order to verify am embodied 16-channel LED driver IC by producing a single IC test board.

• Journal of Advanced Navigation Technology
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• v.22 no.2
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• pp.64-69
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• 2018

Automatic test equipment for field maintenance of aircraft mounted equipment is effective for integrated design when operating a small number of aircraft for special purposes. The integrated automatic test equipment identifies commonly used interfaces and is used for branching or generating routes for each unit under test specific inspection. High-precision signals such as RTD, TC, and analog voltage can cause measurement errors due to conduction resistance during signal branching and connection when generating branches and paths. The measurement error caused by the resistance of the wire leads to a lot of restrictions in designing the equipment to be inspected. In this paper, we propose a method of calibrating highly accurate signals of an integrated automatic inspection equipment that minimizes measurement errors of analog voltage and high - precision signals.

• The Journal of Korean Society for Radiation Therapy
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• v.19 no.1
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• pp.1-5
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• 2007

Purpose: The accuracy and advantages of OBI(On Board Imager) against the conventional method like film and EPID for the setup error correction were evaluated with the analysis of the accumulated data which were produced in the process of setup error correction using OBI. Materials and Methods: The results of setup error correction using OBI system were analyzed for the 130 patients who had been planned for 3 dimensional conformal radiation therapy during March 2006 and May 2006. Two kilo voltage images acquired in the orthogonal direction were fused and compared with reference setup images. The setup errors in the direction of vertical, lateral, longitudinal axis were recorded and calculated the distance from the isocenter. The corrected setup error were analyzed according to the lesion and the degree of shift variations. Results: There was no setup error in the 41.5% of total analyzed patients and setup errors between 1mm and 5mm were found in the 52.3%. 6.1% patients showed the more than 5mm shift and this error were verified as a difference of setup position and the movement of patient in a treatment room. Conclusion: The setup error analysis using OBI in this study verified that the conventional setup process in accordance with the laser and field light was not enough to get rid of the setup error. The KV images acquired using OBI provided good image quality for comparing with simulation images and much lower patients' exposure dose compared with conventional method of using EPID. These advantages of OBI system which were confirmed in this study proved the accuracy and priority of OBI system in the process of IGRT(Image Guided Radiation Therapy).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.15-23
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• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.