• 조명전기설비학회논문지
• /
• 제29권7호
• /
• pp.22-27
• /
• 2015

In this paper, the problem of voltage unbalancing in series-connected multiple electric double-layer capacitors(EDLCs) is studied. Good understanding of this problem is required in order to increase reliability and stability of an energy storage system comprising EDLCs. Existing methods to settle voltage unbalancing cannot mitigate the problem enough for each cell, since most method have been applied to each module. For equalizing between cells, Zener diode which is one of passive method have been well examined in literature. However, Zener have well not used in balancing due to heating problem. In addition, It is difficult to choose Zener diode fitted rating voltage of EDLC, because of its internal resistance. Thus, we proposed passive balancing using Zener diode by analyzing parasitic element of Zener and EDLC. To experimentally confirm the balancing effect, we compared in two occasions which are with and without passive. As a result, proposed passive balancing circuit mitigated unbalanced voltage gap between EDLCs.

• Journal of Electrical Engineering and Technology
• /
• 제13권5호
• /
• pp.1986-1995
• /
• 2018

In this paper, a novel neutral-point voltage balancing scheme for NPC three-level inverters using carrier-based sinusoidal pulse width modulation (SPWM) method is developed. The new modulation approach, based on the obtained expressions of zero sequence voltage in all six sectors, can significantly suppress the low-frequency voltage oscillation in the neutral point at high modulation index and achieve a fast voltage-balancing dynamic performance. The implementation of the proposed method is very simple. Another attractive feature is that the scheme can stably control any voltage difference between the two dc-link capacitors within a certain range without using any extra hardware. Furthermore, the presented scheme is also applicable to the single-phase NPC three-level inverter. It can maintain the neutral-point voltage balance at full modulation index and improve the voltage-balancing dynamic performance of the single-phase NPC three-level inverter. The performance of the proposed strategy and its benefits over other previous techniques are verified experimentally.

• Journal of Power Electronics
• /
• 제17권1호
• /
• pp.96-105
• /
• 2017

In this paper, a hybrid modular multilevel converter (MMC) topology with an improved nearest level modulation method is proposed for medium-voltage high-power applications. The arm of the proposed topology contains N series connected half-bridge submodules (HBSMs), one full-bridge submodule (FBSM) and an inductor. By exploiting the FBSM, half-level voltages are obtained in the arm voltages. Therefore, an output voltage with a 2N+1 level number can be generated. Moreover, the total level number of the inserted submodules (SMs) is a constant. Thus, there is no pulse voltage across the arm inductors, and the SM capacitor voltage is rated. With the proposed voltage balancing method, the capacitor voltage of the HBSM is twice the voltage of the FBSM, and each IGBT of the FBSM has a relatively low switching frequency and an equalized conduction loss. The capacitor voltage balancing methods of the two kinds of SMs are implemented independently. As a result, the switching frequency of the HBSM is not increased compared to the conventional MMC. In addition, according to a theoretical calculation of the total harmonic distortion of the electromotive force (EMF), the voltage quality with the presented method can be significantly enhanced when the SM number is relatively small. Simulation and experimental results obtained with a MMC-based inverter verify the validity of the developed method.

• Journal of Power Electronics
• /
• 제14권2호
• /
• pp.315-323
• /
• 2014

An optimized space vector pulse width modulation (SVPWM) method with common mode voltage elimination and neutral point potential balancing is proposed for an open-end winding induction motor. The motor is fed from both of the ends with two neutral point clamped (NPC) three-level inverters. In order to eliminate the common mode voltage of the motor ends and balance the neutral point potential of the DC link, only zero common mode voltage vectors are used and a balancing control factor is gained from calculation in the strategy. In order to improve the harmonic characteristics of the output voltages and currents, the balancing control factor is regulated properly and the theoretical analysis is provided. Simulation and experimental results show that by adopting the proposed method, the common mode voltage can be completely eliminated, the neutral point potential can be accurately balanced and the harmonic performance for the output voltages and currents can be effectively improved.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2005년도 전력전자학술대회 논문집
• /
• pp.298-301
• /
• 2005

The flying capacitor voltage control of the flying capacitor multi-level inverter (FCMLI) is very important for safe operation. The voltage unbalancing of flying capacitors caused serious problems in safety and reliability of system. In the FCMLI, balancing problem of the flying capacitor has its applications limited. The voltage unbalance is occurred by the difference of each capacitors charging and discharging time applied to FCMLI. This paper investigates and analyzes multi-carrier PWM methods to solve capacitor voltage balancing problem. The Phase-Shift PWM (PSPWM) method that is commonly used, The Modified Carrier-Redistribution PWM (MCRPWM) method and The Saw-Tooth-Rotation PWM (STRPWM) method are discussed and compared with respect to switching state, balancing voltage of capacitors and output waveform. These three PWM methods are analyzed by using a flying capacitor three-level inverter and provided result through simulation. Finally, the harmonics about the output voltages of their methods are compared using the harmonic distortion factor (HDF).

• Journal of Power Electronics
• /
• 제12권4호
• /
• pp.567-577
• /
• 2012

This paper introduces a new scheme to balance the DC bus voltages of a cascaded H-bridge converter which is used as a Distribution Static Synchronous Series Compensator (D-SSSC) in electrical distribution network. The aim of D-SSSC is to control the power flow between two feeders from different substations. As a result of different cell losses and capacitors tolerance the cells DC bus voltage can deviate from their reference values. In the proposed scheme, by individually modifying the reference PWM signal for each cell, an effective balancing procedure is derived. The new balancing procedure needs only the line current sign and is independent of the main control strategy, which controls the total DC bus voltages of cascaded H-bridge. The effect of modulation index variation on the capacitor voltage is analytically derived for the proposed strategy. The proposed method takes advantages of phase shift carrier based modulation and can be applied for a cascaded H-bridge with any number of cells. Also the system is immune to loss of one cell and the presented procedure can keep balancing between the remaining cells. Simulation studies and experimental results validate the effectiveness of the proposed method in the balancing of DC bus voltages.

• 전력전자학회논문지
• /
• 제27권1호
• /
• pp.9-17
• /
• 2022

The series-connected semiconductor devices structure is one way to achieve a high voltage rating. However, a problem with voltage imbalance exists in which different voltages are applied to the series-connected switches. This paper proposed a new voltage balancing technique that controls the turn-off delay time of the switch by adding one bipolar junction transistor to the gate turn-off path. The validity of the proposed method is proved through simulation and experiment. The proposed active gate driver not only enables voltage balancing across a variety of current ranges but also has a greater voltage balancing performance compared with conventional RC snubber methods.

• Journal of Power Electronics
• /
• 제13권2호
• /
• pp.243-249
• /
• 2013

This paper presents a neutral-point voltage balancing method for three-level inverter systems using a time-offset estimation scheme. The neutral-point voltage is balanced by adding a time-offset to the turn-on time of the switches. If an inaccurate time-offset is added, the neutral-point deviation still remains. An accurate time-offset is obtained through the proposed time-offset estimation scheme. This method is implemented without additional hardware, complex calculations, or analysis. The effectiveness of the proposed method is verified by experiments.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1999년도 전력전자학술대회 논문집
• /
• pp.206-209
• /
• 1999

There exists an acute need for high voltage solid-state-switches in a broad area of applications. With the proposed method using simple voltage balancing circuit with series connected IGBTs, it is realized high voltage semiconductor switches with working voltages of several order kilo-volts. The operation principle of the proposed circuit is explained and analyzed. Transient and static voltage-balancing is tested on a experimenta 3kV/45A switch with four series-connected IGBTs.

• 한국산업융합학회 논문집
• /
• 제26권6_2호
• /
• pp.1083-1095
• /
• 2023

Recently, the demand for low-voltage, high-capacity ESS is rapidly increasing due to the revitalization of the e-mobility industry, which is mainly powered by electricity. In addition, the demand for portable power banks is rapidly increasing due to the revitalization of leisure industries such as camping and fishing. The ESS with this structure consists of a small number of series cells and many parallel cells, resulting in a system with a large rated current. Therefore, the number of power devices for cell balancing configured in series is small, but a balancing device with a large current capacity is required. Construction of a constant temperature device in such a low-voltage, high-current ESS is difficult due to economic issues. The demand for an active balancing system that can solve the passive balancing heating problem is rapidly increasing. In this paper, propose a power feedback fly-back topology that can solve the balancing heating problem. The characteristic of the proposed topology is that a series-connected voltage sharing voltage is used as the input of the flyback converter, and the converter output is connected to one transformer. In this structure, the converter output for cell voltage balancing shares magnetic flux through one high-frequency transformer, so the cell voltage connected to the converter automatically converges to the same voltage.