• 조명전기설비학회논문지
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• 제18권2호
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• pp.68-74
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• 2004

본 논문에서는 고조파를 저감시키고 출력파형 개선을 위한 방법으로 입력측 DC링크 전압의 조합을 이용한 새로운 하이브리드형 멀티레벨 인버터를 제안한다. 제안한 인버터는 단상 풀-브릿지 인버터 모듈로 구성된 3개의 H-bridge cell로 구성되어 있다. 2개의 풀-브릿지 모듈은 레벨생성을 위해 사용되고 나머지 하나의 모듈은 PWM 스위칭 동작에 사용되어진다. 레벨 생성을 위한 인버터에 의해 9레벨이 생성되고 PWM 동작을 위한 인버터에 의해 2레벨이 더해지게 되어 결과적으로 총 11레벨의 출력전압을 생성시킬 수 있다. 제안한 시스템의 기본적인 동작원리를 상세하게 설명하고 PSpice 시뮬레이션과 시작품을 이용한 실험을 통해 타당성을 증명할 수 있었다.

• 전자공학회논문지A
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• 제31A권7호
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• pp.110-116
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• 1994

In this paper a Duty Effective Overlap Scanning method (DEOS) for the improvement of driving efficiency of LC displays which have the RMS voltage responding characteristics is proposed and new processing method of data signals for optimum application of this method is also proposed. Proposed method has a few advantages such as the increment of duty ratio the increment of driving power loaded on LC cell and the decrement of RMS voltage error rate caused by signal attenuation on electrodes composing of display when compared with the conventional method which is called as optimum voltage amplitude selection method. And also by adopting new data signal processing method which has 3 kinds of voltage levels additional advantage much improving crosstalk phenomenon which is the most serious problems of simple matrix structured display is obtained. For the characteristic estimation new mathematical representation for new overlap scanning method and data signal processing method are induced and defined. And by the defined formula and simulation the characteristics of the proposed method and the conventional method are compared and analyzed. As a result of estimation this new method being able to optimize the overlap rate of scan signal and using 3 levels of data signals has the characteristic which can improve the driving efficiency of LC displays.

• Journal of Power Electronics
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• 제16권5호
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• pp.1706-1715
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• 2016

In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results.

• Journal of Power Electronics
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• 제16권6호
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• pp.2139-2149
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• 2016

In this study, a new type of cascaded modular multilevel inverters (CMMLIs) is presented which is able to produce a considerable number of output voltage levels with a reasonable number of components. Accordingly, each series stage of the proposed CMMLI is comprised of two same basic units that are connected with each other through two unidirectional power switches without aiming any of the full H-bridge cells. In addition, since the potentiality for generating a higher number of output voltage levels in CMMLIs hinges on the magnitude of the dc voltage sources used in each series unit, in the rest of this paper, four different algorithms for determining an appropriate value for the dc sources' magnitude are also presented. In the following, a comprehensive topological analysis between some CMMLI structures reported in the literature and proposed structure along with several simulation and experimental results will be also given to validate the lucrative benefits and viability of the proposed topology.

• 전기학회논문지
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• 제64권11호
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• pp.1564-1570
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• 2015

This paper intends to suggest a sensing circuit of PWM voltage for a motor emulator operated in the inverter. In the emulation of the motor using a power converter, it is necessary to measure instantaneous voltage at the PWM voltage loaded from the inverter. Using a filter can generate instantaneous voltage, while it is difficult to follow the rapidly changing inverter voltage caused by the propagation delay and signal attenuation. The method of measuring the duty of PWM using FPGA can generate output voltage from the one-cycle delay of PWM, while the cost of hardware is increasing in order to acquire high precision. This paper suggests a PWM voltage sensing circuit using the analogue system that shows high precision, one-cycle delay of PWM and low-cost hardware. The PWM voltage sensing circuit works in the process of integrating input voltage for valid time by comparing levels of three-phase PWM input voltage, and produce the output value integrated at zero vector. As a result of PSIM simulation and the experiment with the produced hardware, it was verified that the suggested circuit in this paper is valid.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1337-1344
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• 2013

This paper presents a simplified modulation strategy for the three-leg VSI fed two-winding induction motor. The strategy provides independent unbalanced voltage control for the main and auxiliary windings. This make the motor can be reversed rotation through the range of motor speed operation without limitation of voltage boost of the auxiliary winding. To study the advantages of the proposed drive, the experimental results such as voltage stresses, hysteresis band of the currents in locus, and also acoustic noise levels of the three-leg VSI are compared with those of the conventional two-leg topology. The results obviously show that the proposed technique achieves superior performance compared with the traditional scheme in case of dramatic increase of DC bus utilization, effective reduction of harmonic voltages content, and also significant enhancement of motor efficiency.

• 제어로봇시스템학회논문지
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• 제16권2호
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• pp.145-150
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• 2010

This paper deals with reduction of torque ripple in a brushless DC motor with input voltage control. The commutation torque ripple can be controlled with varying input voltage, but cogging torque is independent on it. So, in this paper a strategy for minimizing torque ripple is proposed by offsetting the cogging torque with deliberate voltage control. The optimal condition is determined with variable voltage levels and advance angles. As results, it is shown that the method causes 63% decrease of torque ripple.

• Journal of Power Electronics
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• 제10권2호
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• pp.138-145
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• 2010

This paper presents a single phase multilevel inverter for using as a voltage harmonic source. First, a single phase multilevel inverter system is presented and the structural parts of the inverter are described. In order to obtain multilevel output voltage waveforms, a switching strategy based on calculating switching angles is explained and an improved formula for determining switching angles is given. Simulation and experimental results of multilevel voltage waveforms are given for 15, 31 and 127 levels. The proposed topology does not only produce output voltages with low THD values. It also produces the required harmonic components on the output voltage. For this purpose, equations for switching angles are constituted and the switching functions are obtained. These angles control the output voltage as well as provide the required specific harmonics. The proposed inverter structure is simulated for various functions with the required harmonic components. The THD values of the output voltage waves are calculated. The simulated functions are also realized by the proposed inverter structure. By using a harmonic analyzer, the harmonic spectrums, which belong to the output voltage forms, are found and the THD values are measured. Simulation and experimental results are given for the specific functions. The proposed topology produces perfectly suitable results for obtaining the specific harmonic components. Therefore, it is possible to use the structure as a voltage harmonic source in various applications.

• 한국산업융합학회 논문집
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• 제20권4호
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• pp.257-263
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• 2017

The following thesis researched into the characteristics of electrolytic ion water with different levels of electrical conductivity by adding NaCl into tap water which is for experimental use in multi-layered electrolytic ion water generator. Electrolytic ion water is generated by underwater electrolysis and the electrolysis generator has a simple structure, is easy to control and is highly utilized in industries. Electrolytic ion water is useful in many areas since it has a superior sterilizing power, has no possibility of secondary pollution itself as water and removes active oxygen. In the experiment, we used tap water with NaCl excluded and water with three different levels of electrical conductivity by changing NaCl concentration levels into three levels. The features of current and voltage in electrolytic ion water represented a form of quadric instead of the linear characteristic following ohm's law. As well, as the electric conductivity of water and applied voltage increased, we were able to generate much stronger acid water and alkali water.

• 조명전기설비학회논문지
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• 제30권3호
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• pp.1-8
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• 2016

In this paper, we proposed a new driving scheme to reduce the motion blur and save the power for OLEDs(organic light emitting diodes). We adopted a DVS (dynamic voltage scaling) method to reduce power consumption and the division of TV field to improve motion blur. In the proposed scheme, BEW (Blur Edge Width) was decreased to the ratio of 1/4 compared to the conventional scheme under the optimal conditions. In this scheme, the gray levels to which the DVS method can be applied were divided into much smaller groups depending on the number of subfields. Therefore, our scheme does not guarantee less power consumption for every image compared to the conventional scheme. However, the new scheme can move the gray levels adopting the DVS to higher gray levels. Thus, we can save power even when having images at high gray levels.