• 대한전기학회논문지:전력기술부문A
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• 제53권3호
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• pp.161-167
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• 2004

Zone 3 of the distance relay is used to provide the remote back-up protection in case of the failure of the primary protection. However, the risk lot mal-operations under stressed conditions such as heavy loading, voltage and transient instability is usually high. Zone 3 is used in combination with the derivatives of the voltage, and current, etc to prevent mal-operations. Sometimes, the impedance characteristics that restrict the tripping area of relay are used to avoid the mal-operations due to load encroachment. This paper presents a novel Zone 3 scheme based on combining the steady-state components (i.e. 60Hz) and the transient components (TCs) using a state diagram that visualizes the sequence of studies that emanate from the sequence of events. The simulation results show that the novel zone 3 distance relay elements using the proposed method operates correctly for the various events.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.79-99
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• 2010

Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-k dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trap-induced threshold voltage shift (${\Delta}V_t$), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-$\kappa$ gate dielectric devices.

• Journal of Power Electronics
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• 제17권5호
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• pp.1298-1307
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• 2017

The constant on-time current-mode controlled (COT-CMC) switching dc-dc converter is stable, with no subharmonic oscillation in its current loop when a voltage ripple in its outer voltage loop is ignored. However, when its output capacitance is small or its feedback gain is high, subharmonic oscillation may occur in a COT-CMC buck converter with a proportional-integral (PI) compensator. To investigate the subharmonic instability of COT-CMC buck converters with a PI compensator, an accurate reduced-order asynchronous-switching map model of a COT-CMC buck converter with a PI compensator is established. Based on this, the instability behaviors caused by output capacitance and feedback gain are investigated. Furthermore, an approximate instability condition is obtained and design-oriented stability boundaries in different circuit parameter spaces are yielded. The analysis results show that the instability of COT-CMC buck converters with a PI compensator is mainly affected by the output capacitance, output capacitor equivalent series resistance (ESR), feedback gain, current-sensing gain and constant on-time. The study results of this paper are helpful for the circuit parameter design of COT-CMC switching dc-dc converters. Experimental results are provided to verify the analysis results.

• 한국조명전기설비학회지:조명전기설비
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• 제9권1호
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• pp.37-46
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• 1995

최근의 전력계통은 대규모 복잡화 되어가고 장거리 대용량 송전이 증대함에 따라 안정도 해석에서 부하특성을 고려한 해석은 중요한 과제이다. 본 논문은 전력계통의 유도부하가 전력계통의 전압에 미치는 영향을 조사 분석한 논문으로 그 주요내용은 부하모선에 연결된 부하중에서 유도 전동기 부하의 비율이 크거나 유도전동기 부하의 관성정수가 적은 경우가 전압 불안정 현상에 미치는 영향이 크며, 유도전동기 부하가 클 경우는 그 부하가 연결된 회로의 일부 개로시 즉 단순한 계통의 회로 변경시에도 전압불안정 현상을 일으킬 수 있다. 이 전압 불안정 현상은 부하의 응동특성에 따라 계통에 적정용량의 전력용 콘덴서를 투입함으로써 방지할 수 있다.

• 전기학회논문지
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• 제62권7호
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• pp.943-949
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• 2013

Recently, an electric vehicle (EV) has been become a huge issue in the automotive industry. The EV has many electrical units: electric motors, batteries, converters, etc. The DC distribution power system (DPS) is essential for the EV. The DC DPS offers many advantages. However, multiple loads in the DC DPS may affect the severe instability on the DC bus voltage. Therefore, a voltage bus conditioner (VBC) may use the DC DPS. The VBC is used to mitigate the voltage transient on the bus. Thus, a suitable control technique should be selected for the VBC. In this research, Current controller with fixed switching frequency is designed and applied for the VBC. The DC DPS consist of both a resistor load and a boost converter load. The load variations cause the instability of the DC DPS. This instability is mitigated by the VBC. The simulation results by Matlab simulink and experimental results are presented for validating the proposed VBC and designed control technique.

• 조명전기설비학회논문지
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• 제12권3호
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• pp.132-138
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• 1998

최근의 자가발전기를 보유한 대용량 수용가에서는 자체의 전력계통올 안정하게 유지하기 위한 명가 방법으로서 안정도 해석올 통한 계통의 문제점을 파악하는 것은 중요한 과제이다. 본 논문은 전력계통에 있어서 대전력계통(한전계통)측의 3상 단락고장시 고장 지속 시간에 따른 자가 발전을 보유한 수용가 전력계통의 전압에 미치는 영향을 조사 분석한 논문으로 한전계통측의 고장 지속 시간에 따라 수용가 계통의 발전기 및 동기기가 불안정하게 된다. 이러한 불안정현상은 후비보호 계전기(저전압 계전기)의 적절한 시간 설정으로 한전계통과 분리하고 수용가의 부하를 차단하므로써 안정도를 증진시킬 수 있다.

• 대한전기학회논문지:전력기술부문A
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• 제53권3호
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• pp.175-181
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• 2004

The protection against transient instability and consequent out-of-step condition is a major concern for the utility industry. Unstable system may cause serious damage to system elements such as generators and transmission lines. Therefore, out-of-step detection is essential to operate a system safely. The detection of out-of-step is generally based upon the rate of movement of the apparent impedance. However such relay monitors only the apparent impedance which may not be sufficient to correctly detect all forms of out-of-step and cannot cope with out-of-step for a more complex type of instability such as very fast power swing. This paper presents the out-of-step detection algorithm using voltage frequency deviation. The digital filters based on discrete Fourier transforms (DFT) to calculate the frequency of a sinusoid voltage are used, and the generator angle is estimated using the deviation of the calculated frequency component of the voltage. The proposed out-of-step algorithm is based on the assessment of a transient stability using equal area criterion. The proposed out-of-step algorithm is verified and tested by using EMTP MODELS.

• 한국전기전자재료학회논문지
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• 제23권7호
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• pp.545-549
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• 2010

Low-frequency noise (1/f noise) has been measured in order to analyze the Vth instability of ZnO TFTs having two different active layer thicknesses of 40 nm and 80 nm. Under electrical stress, it was found that the TFTs with the active layer thickness of 80 nm shows smaller threshold voltage shift (${\Delta}V_{th}$) than those with thickness of 40 nm. However the ${\Delta}V_{th}$ is completely relaxed after the removal of DC stress. In order to investigate the cause of this threshold voltage instability, we accomplished the 1/f noise measurement and found that ZnO TFTs exposed the mobility fluctuation properties, in which the noise level increases as the gate bias rises and the normalized drain current noise level($S_{ID}/{I_D}^2$) of the active layer of thickness 80 nm is smaller than that of active layer thickness of thickness 40 nm. This result means that the 80 nm thickness TFTs have a smaller density of traps. This result correlated with the physical characteristics analysis performmed using XRD, which indicated that the grain size increases when the active layer thickness is made thicker. Consequently, the number of preexisting traps in the device increases with decreasing thickness of the active layer and are related closely to the $V_{th}$ instability under electrical stress.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.87-97
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• 2013

Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) are critical circuit reliability issues in highly scaled CMOS technologies. In this paper, we analyze the impacts of NBTI and PBTI on SRAM $V_{MIN}$, and present a design solution for mitigating the impact of NBTI and PBTI on SRAM $V_{MIN}$. Two different types of SRAM $V_{MIN}$ (SNM-limited $V_{MIN}$ and time-limited $V_{MIN}$) are explained. Simulation results show that SNM-limited $V_{MIN}$ is more sensitive to NBTI while time-limited $V_{MIN}$ is more prone to suffer from PBTI effect. The proposed NBTI/PBTI-aware control of wordline pulse width and woldline voltage improves cell stability, and mitigates the $V_{MIN}$ degradation induced by NBTI/PBTI.

• 전력전자학회논문지
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• 제15권1호
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• pp.43-51
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• 2010

본 논문에서는 고전압 전동기 가변속 장치인 H-브릿지 멀티레벨(H-Bridge Multi-Level; HBML) 인버터를 이용한 유도 전동기 벡터 제어시 인버터의 출력 전압 위상 지연 현상을 해석하고 전류 제어기의 보상 기법을 제시하였다. Phase-Shifted Pulse Width Modulation (PSPWM) 기법을 적용한 HBML 인버터는 개별 인버터 모듈이 독립적으로 동작할 수 있어서 확장성과 모듈화 능력이 향상되는 장점이 있다. 그러나 이러한 PSPWM을 적용한 HBML 인버터는 기준 전압과 실제 전압 사이에 위상 차이가 있기 때문에 출력 주파수에 대한 샘플링 주파수의 비율이 충분하지 않은 고속 영역에서 전류 제어기를 불안정하게 하는 원인이 된다. 전류 제어기의 불안정성은 기준 전압과 출력 전압의 위상 차이를 보상하는 제안된 방법을 추가함으로써 제거하였다. 본 방법은 인버터의 스위칭 주파수가 낮고, 전동기 속도가 높은 조건에서 PSPWM을 이용한 HBML 인버터 시스템에 효과적이며, 13레벨로 구성된 HBML 인버터로 구동되는 6,600[V] 1,400[kW] 유도전동기 실험을 통해 제안된 방법의 타당성을 입증하였다.