• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.2
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• pp.175-181
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• 2024

In electrical power substations, bulky iron-core potential transformers (PTs) are installed in a tank of gas-insulated switchgear (GIS) to measure system voltages. This paper proposed a low-power voltage transformer (LPVT) that can replace the conventional iron-core PTs in response to the demand for the digitalization of substations. The prototype LPVT consists of a capacitive voltage divider (CVD) which is embedded in a spacer and an impedance matching circuit using passive components. The CVD was fabricated with a flexible PCB to acquire enough insulation performance and withstand vibration and shock during operation. The performance of the LPVT was evaluated at 80%, 100%, and 120% of the rated voltage (38.1 kV) according to IEC 61869-11. An accuracy correction algorithm based on LabVIEW was applied to correct the voltage ratio and phase error. The corrected voltage ratio and phase error were +0.134% and +0.079 min., respectively, which satisfies the accuracy CL 0.2. In addition, the voltage ratio of LPVT was analyzed in ranges of -40~+40℃, and a temperature correction coefficient was applied to maintain the accuracy CL 0.2. By applying the LPVT proposed in this paper to the same rating GIS, it can be reduced the length per GIS bay by 11%, and the amount of SF6 by 5~7%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.530-534
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• 2002

In the thesis, For improving the Stability of VCHRO(Voltage Controlled Hair-pin Resonator Oscillator) the new structure using the parallel feedback of the second harmonic is proposed for self-phase locking effect. This module is composed of wilkinson divider, frequency doubler, directional coupler, and bandpass filter using a hair-pin resonator, which are integrated into miniaturized hybrid circuit. The module exhibits output power of 2.5 dBm at 19.5 GHz, -29.83 dBc fundamental frequency suppression and -76.52 dBc/Hz phase noise at 10 kHz offset frequency from carrier of center frequency 19.5 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.302-312
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• 2012

In this paper, small-area and high-reliability design techniques of a 512-bit EEPROM are designed for UHF RFID tag chips. For a small-area technique, there are a WL driver circuit simplifying its decoding logic and a VREF generator using a resistor divider instead of a BGR. The layout size of the designed 512-bit EEPROM IP with MagnaChip's $0.18{\mu}m$ EEPROM is $59.465{\mu}m{\times}366.76{\mu}m$ which is 16.7% smaller than the conventional counterpart. Also, we solve a problem of breaking 5V devices by keeping VDDP voltage constant since a boosted output from a DC-DC converter is made discharge to the common ground VSS instead of VDDP (=3.15V) in getting out of the write mode.

• Journal of IKEEE
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• v.23 no.3
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• pp.858-864
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• 2019

A clock system is proposed to eliminate data loss due to frequency difference between sensor nodes in a sensor utility network. The proposed clock system for each sensor node consists of a bust clock-data recovery (CDR) circuit, a digital phase-locked loop outputting a 32-phase clock, and a digital frequency synthesizer using a programmable open-loop fractional divider. A CMOS oscillator using an active inductor is used instead of a burst CDR circuit for the first sensor node. The proposed clock system is designed by using a 65 nm CMOS process with a 1.2 V supply voltage. When the frequency error between the sensor nodes is 1%, the proposed burst CDR has a time jitter of only 4.95 ns with a frequency multiplied by 64 for a data rate of 5 Mbps as the reference clock. Furthermore, the frequency change of the designed digital frequency synthesizer is performed within one period of the output clock in the frequency range of 100 kHz to 320 MHz.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1969-1971
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• 2004

For evaluation of partial discharge performances of electrical power appratus such as Insulator, circuit breaker and transformer and so on, Partial discharge measuring system(ERA) consisted of PD detector including amplifier, coupling capacitor, PD calibrator and voltage divider are used PD measuring system is very important factor which affect the test result and show reliability of test result in test laboratory, In this paper, we describe tracebility and uncertainty of PD measuring system in test laboratory based on IEC 60270.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1793-1795
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• 2004

지금까지 변전소나 개폐소에서 전류, 전압을 계측하는 수단으로서 주로 철심과 권선으로 구성되어진 변류기(CT), 계기용 변압기(PT, PD)가 사용되어 왔다 최근, 2차측의 계측기나 보호 Relay의 Digital화가 진전되어, 또한 이것을 Digital Network으로 종합한 Intelligent 변전소의 구축이 검토되어짐에 따라 Digital Network에 대응한 신형 CT, VD가 요구되어 지고 있다. 상기와 같은 요구로 인해 당사에서는 CT는 검출부에 Rogowski Coil을 적용하며 그 후단에 적분기를 설치하였으면, VD는 검출부에 중간 전극을 이용해서 분압하는 방식인 Capacitive Voltage Divider를 사용하고 증폭기를 삽입하여, 각각 요구되는 전압 신호를 얻었다. 이러한 신형 CT/VD의 적용으로 종래의 CT/PT가 차지하는 공간이 필요 없게 되어 컴팩트한 GIS의 구조가 능하게 되어 있다.

• Journal of IKEEE
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• v.13 no.2
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• pp.248-252
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• 2009

In this paper, analysis of a noise factor and an effective power strategy for the OLED dc-dc converter are described. One of the main reasons that one may not design the OLED power for dc-dc converter is that OLED's panel noise is composed of FFN(Frame Frequency Noise) and LFN(Line Frequency Noise). Into the bargain, FFN is caused by both the dc-dc (circuit) and driving circuit. It is hard to get rid of FFN, baeause FFN has very little results value for our ears. LFN is adjusted by analog compensation value. Actually, that is more important problem than FFN. It is known that voltage divider for OLED's mode variation is not good for compact power design. In the end, a circuit design for understanding OLED's noise and a novel muti-channel dc-dc converter were presented.

• ETRI Journal
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• v.37 no.1
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• pp.26-31
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• 2015

Axial-ratio (AR) bandwidth enhancement is achieved for a circularly polarized (CP) cylindrical dielectric resonator antenna (DRA) using a wideband hybrid coupler (WHC) combined with dual probe feed. The presented WHC, comprised of a Wilkinson power divider and a wideband $90^{\circ}$ shifter, delivers good characteristics in terms of 3 dB power splitting and consistent $90^{\circ}$ (${\pm}5^{\circ}$) phase shifting over a wide bandwidth. In turn, the proposed CP DRA, for the employment of the WHC, in place of conventional designs, provides a significant enhancement on AR bandwidth and impedance matching. The antenna prototype with the WHC exhibits a 3 dB AR bandwidth of 48.66%, an impedance bandwidth of 52.5% for voltage standing wave ratio (VSWR) ${\leq}2$, and a bandwidth of 44.66% for a gain of no less than 3 dBi. Experiments demonstrate that the proposed WHC is suitable for broadband CP DRA design.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.158-162
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• 2015

A low phase noise CMOS voltage controlled oscillator(VCO) for multi-band/multi-standard RF Transceivers is presented. For both wide tunability and low phase noise characteristics, Hybrid inductor which uses both bondwire inductor and planar spiral inductor in the same area, is proposed. This approach reduces inductance variation and presents high quality factor without custom-designed single-turn inductor occupying large area, which improves phase noise and tuning range characteristics without additional area loss. An LC VCO is designed in a 0.13um CMOS technology to demonstrate the hybrid inductor concept. The measured phase noise is -121dBc/Hz at 400KHz offset and -142dBc/Hz at 3MHz offset from a 900MHz carrier frequency after divider. The tuning range of about 28%(3.15 to 4.18GHz) is measured. The VCO consumes 7.5mA from 1.3V supply and meets the requirements for GSM/EDGE and WCDMA standard.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.523-526
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• 2001

In this paper, we design and fabricate the high-efficiency and low-power switched-capacitor DC-DC converter. This converter consists of internal oscillator, output driver and output switches. The internal oscillator has 100kHz oscillation frequency and the output switches composed of one pMOS transistor and three nMOS transistors. According to the configuration of two external capacitors, the converter has three functions that are the Inverter, Doubler and Divider. The proposed converter is fabricated through the 0.8$\mu\textrm{m}$ 2-poly, 2-metal CMOS process. The simulation and experimental result for fabricated IC show that the proposed converter has the voltage conversion efficiency of 98% and power efficiency more than 95%.