• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.949-952
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• 2009

In this paper, a watermarking method based on the trellis code with multi-layer is proposed. An image is divided $8{\times}8$ block with no overlapping, and compute the discrete cosine transform(DCT) of each block, and the 12 medium-frequency AC terms from each block are extracted. Next it is compared with gaussian random vectors with zero mean and unit variance. As these processing, the embedding vectors with minimum linear correlation can be obtained by Viterbi algorithm at each layer of trellis coding. To evaluate the performance of proposed method, the average bit error rate of watermark message is calculated from different several images.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.9 no.1
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• pp.115-126
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• 1999

As the processing speed of communication and computer system has been improved, high speed data processing is required to correct error of data. In this paper, decoding algorithm which is applicable to the wireless communication system is proposed and encoder and decoder are designed by using the proposed decoding algorithm. We design the encoder and decoder by using the VHDL(VHSIC Hardware Description Language) and simulate the designed encoder and decoder by using V-system. Designed algorithm is synthesized by using synopsys tools and is made to one chip by means of XILINX XC4010EPC84-4. When 20MHz was used as the input clock, data arrival time was 29.20ns and data require time was 48.70ns.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.188-194
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• 2007

In order to become ubiquitous world, the compatibility of wireless machines has become the significant characteristic of a communication terminal. Thus, SDR is the most necessary technology and standard. However, among the environment which has different communication protocol, it's difficult to make a terminal with only hardware using ASIC or SoC. This paper suggests the processor that can accelerate several communication protocol. It can be connected with main-processor, and it is specialized PHY layer of network The C-program that is modeled with the wireless protocol IEEE802.11a and IEEE802.11b which are based on widely used modulation way; OFDM and CDM is compiled with ARM cross compiler and done simulation and profiling with Simplescalar-Arm version. The result of profiling, most operations were Viterbi operations and complex floating point operations. According to this result we suggested a co-processor which can accelerate Viterbi operations and complex floating point operations and added instructions. These instructions are simulated with Simplescalar-Arm version. The result of this simulation, comparing with computing only one ARM core, the operations of Viterbi improved as fast as 4.5 times. And the operations of complex floating point improved as fast as twice. The operations of IEEE802.11a are 3 times faster, and the operations of IEEE802.11b are 1.5 times faster.

• Journal of KIISE:Software and Applications
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• v.35 no.5
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• pp.313-324
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• 2008

A sentence reduction is the information compression process which removes extraneous words and phrases and retains basic meaning of the original sentence. Most researches in the sentence reduction have required a large number of lexical and syntactic resources and focused on extracting or removing extraneous constituents such as words, phrases and clauses of the sentence via the complicated parsing process. However, these researches have some problems. First, the lexical resource which can be obtained in loaming data is very limited. Second, it is difficult to reduce the sentence to languages that have no method for reliable syntactic parsing because of an ambiguity and exceptional expression of the sentence. In order to solve these problems, we propose the sentence reduction method which uses templates and POS(part of speech) information without a parsing process. In our proposed method, we create a new sentence using both Sentence Reduction Templates that decide the reduction sentence form and Grammatical POS-based Reduction Rules that compose the grammatical sentence structure. In addition, We use Viterbi algorithms at HMM(Hidden Markov Models) to avoid the exponential calculation problem which occurs under applying to Sentence Reduction Templates. Finally, our experiments show that the proposed method achieves acceptable results in comparison to the previous sentence reduction methods.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.26-34
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• 2002

Mobile telecommunication systems such as IS-95 and IMT-2000 employ frame based communication using frames up to 20 msec in length and the receiving end has to store the whole frome before it is being processed. The size of the frame buffer ofter dominates those of the processing unit such as soft decision Viterbi decoder. The frame buffer for IMT-2000, for example, has to be increased 80 times as large as that of IS-95. One of the parameters deciding the number of bits in a frame will be obviously the number of bits in soft quantization. Start after striking space key 2 times. This paper has studied a new aspect of offset and quantization step size on BER performance and proposes a new 3-bit soft quantization algorithm which shows similar performance as that of 4-bit soft decision Viterbi receiver. The optimal offset values and step sizes for the other practical quantization levels ---16, 8, 4, 2--- have also been found. In addition, a new optimal symbol metric table has been devised which takes the accumulation value of various repeated signals and produces a rescaled 3-bit valu.tart after striking space key 2 times.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.14-23
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• 2002

Two implementation methods for SOVA (Soft Output Viterbi Algorithm)of Turbo decoder are applied and verfied. The first method is the combination of a trace back (TB) logic for the survivor state and a double trace back logic for the weight value in two-step SOVA. This architecure of two-setp SOVA decoder allows important savings in area and high-speed processing compared with that of one-step SOVA decoding using register exchange (RE) or trace-back (TB) method. Second method is adjusting the reliability value with a scaling factor between 0.25 and 0.33 in order to compensate for the distortion for a rate 1/3 and 8-state SOVA decoder with a 256-bit frame size. The proposed schemes contributed to higher SNR performance by 2dB at the BER 10E-4 than that of SOVA decoder without a scaling factor. In order to verify the suggested schemes, the SOVA decoder is testd using Xillinx XCV 1000E FPGA, which runs at 33.6MHz of the maximum speed with 845 latencies and it features 175K gates in the case of 256-bit frame size.

• MALSORI
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• no.52
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• pp.101-110
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• 2004

This paper proposes a new confidence measure for utterance verification with posterior probability approximation. The proposed method approximates probabilistic likelihoods by using Viterbi search characteristics and a clustered phoneme confusion matrix. Our measure consists of the weighted linear combination of acoustic and phonetic confidence scores. The proposed algorithm shows better performance even with the reduced computational complexity than those utilizing conventional confidence measures.

• ETRI Journal
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• v.25 no.1
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• pp.1-8
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• 2003

This paper introduces an efficient iterative decoding method for high-dimensional block turbo codes. To improve the decoding performance, we modified the soft decision Viterbi decoding algorithm, which is a trellis-based method. The iteration number can be significantly reduced in the soft output decoding process by applying multiple usage of extrinsic reliability information from all available axes and appropriately normalizing them. Our simulation results reveal that the proposed decoding process needs only about 30% of the iterations required to obtain the same performance with the conventional method at a bit error rate range of $10^{-5}\;to\;10^{-6}$.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.77-80
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• 2000

In this paper, we implemented the voice modem using the multicarrier DS-CDMA in powerline channels. Both TMS320C5402 of Texas Instrument and FPGA FLEX 10K EPF10K100ARC240 of ALTERA are used to realize the proposed system. For robustness in the powerline channel, we used multicarrier DS-CDMA modulation, convolutional encoding/Viterbi decoding, and interleaving. Finally, we showed satisfactory performance in the laboratory experiment.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.865-868
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• 2001

TCM offers considerable coding gains without compromising bandwidth or signal power. But TCM decoder is more complex than convolutional Viterbi decoder. Because, the number of branches exponentially increased by the constraint length and input symbol bits. The parallelism of ACS and memory management technique of SPMM is one of the important factor for speed-up and hardware complexity. This paper proposes a multi-processing technique of ACS and also gives a memory management technique of SPMM in TCM decoders.