• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.76-91
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• 1996

In this paper, we proposed the new medium access control protocol for the virtual token bus netowrk. The network is applied to inter-processor communication network of large capacity digital switching system and digital mobile system with distributed control architecture. in the virtual token bus netowrk, the existing medium access control protocols hav ea switchove rtime overhead when traffic load is light or asymmetric according ot arbitration address of node that has message to send. The proposed protocol optimized average message delay using cyclic bus access chain to exclude switchover time of node that do not have message to send. Therefore it enhanced bus tuilization and average message delay that degrades the performance of real time communication netowrks. It showed that the proposed protocol is more enhacned than virtual token medium access control protocol and virtual token medium access control protocol iwth reservation through performance analysis.

• Journal of Power System Engineering
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• v.15 no.2
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• pp.19-24
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• 2011

In this study, a control method of MR(magneto-rheological) damper for a cruise bus is investigated. A virtual dynamic damper and a sky-hook algorithm are employed to control the damping characteristics of MR damper. Coefficients for a virtual dynamic damper are determined through the parameter identification. A quarter car model of a cruise bus is established by using ADAMS/Car program for the computer simulation. Sine wave excitation and random excitation are used to compare the controlled MR damper with the passive damper. From the simulation results, the performance of MR damper with a virtual dynamic damper is better than that of the passive damper.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.74-76
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• 2001

When a Bus voltage is low, the Load-Flour is generally blown up. If Bus voltage is normalized. the convergence of Load-flow is improved. This paper introduces virtual bus with tap. In that case, the Bus admittance will be considered. And the convergence of Load-Flow in applying virtual bus is debated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.132-140
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• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.883-885
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• 2001

Wave Pipelining(WP) 기법을 적용한 가상버스(Virtual Bus) 네트워크 구조는 병렬 컴퓨팅에서 중요한 메시지의 긴급성을 효과적으로 지원한다. 우리는 효율적인 통신을 지원하는 가상버스에 적합하도록 MPI를 설계, 구현(MPI/VBus)하였다. 또한, MPI/Vbus와 디바이스 드라이버가 메시지 큐들을 커털 영역에서 공유하도록 설계함으로써 사용자 레벨 통신(User Level Communication)을 쉽게 구현할 수 있도록 했다.

• Journal of Electrical Engineering and Technology
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• v.5 no.4
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• pp.511-521
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• 2010

This paper presents a new algorithm to determine accurate bus-wise transmission loss allocation utilizing path-integrals dictated by the transaction strategy. For any transaction strategy, the total sum of the allocated transmission losses of all buses is equal to the actual loss given by the AC power-flow calculation considering the distributed slack. In this paper, the bus-wise allocation of the transmission loss is calculated by integrating the differential loss along a path determined by the transaction strategy. The proposed algorithm is also compared with Galiana's method, which is the well-known transmission loss allocation algorithm based on integration. The performance of the proposed algorithm is evaluated by case studies carried out on the WSCC 9-bus, IEEE 14-bus, New England 39-bus, and IEEE 118-bus systems. The simulation results show that the proposed algorithm is fast and accurate with a large step size.

• Journal of the Korea Society for Simulation
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• v.8 no.4
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• pp.9-24
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• 1999

We describe a heterogeneous simulation framework, so called DEVS-HLA, in which conventional simulation models and the DEVS (Discrete Event System Specification) models are interoperable. DEVS-HLA conceptually consists of three layers: model layer, DEVS BUS layer, and HLA (High Level Architecture) layer. The model layer has a collection of heterogeneous simulation models, such as DEVS, CSIM, SLAM, and so on, to represent various aspects of a complex system. The DEVS BUS layer provides a virtual software bus, DEVS BUS, so that such simulation models can communicate with each other. Finally, the HLA layer is employed as a communication infrastructure, which supports several good features for distributed simulation. The DEVS BUS has been implemented on the HLA/RTI (Run-Time Infrastructure) and a simple example of a flexible manufacturing system has been developed to validate the DEVS-HLA.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.8
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• pp.1145-1153
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• 2015

The paper analyzes reactive power flow characteristic in power system by reactive power tracing. In addition, virtual buses are inserted in the algorithm to consider losses of transmission lines, and shunt capacitor treated as a reactive power generator. The results of simulation are analyzed by two points of view. The one is load’s point of view and another is generator’s point of view. Classic purpose of the reactive power tracing consists in the reactive power pricing. However, it is significantly used to select vulnerable area about line outage in this paper. To find the vulnerable area, reactive power tracing variations between pre-contingency and post-contingency are calculated at all load buses. In heavily load area, buses which has highest variation become the most vulnerable bus. This method is applied to the IEEE 39-bus system. It is compared with voltage variation result and VQ-margin to verify its effect.

• Journal of applied mathematics & informatics
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• v.28 no.1_2
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• pp.539-551
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• 2010

Low scalability and power efficiency of the shared bus in SoCs is a motivation to use on chip networks instead of traditional buses. In this paper we have modified the Orion power model to reach an analytical model to estimate the average message energy in K-Ary n-Cubes with focus on the number of virtual channels. Afterward by using the power model and also the performance model proposed in [11] the effect of number of virtual channels on Energy-Delay product have been analyzed. In addition a cycle accurate power and performance simulator have been implemented in VHDL to verify the results.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.12
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• pp.1434-1440
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• 2011

In this paper, we assessed muscular activities of lower limbs and foot pressure for car and bus drivers according to operating three electronic pedals that we developed. To analyze drivers' physical exhaustion, muscular fatigue of lower limbs was evaluated. Eleven car drivers and six urban bus drivers were participated in this experiment. The virtual driving system was used for the real driving environment. The virtual driving system was comprised of a spring seat, a steering wheel, pedals (clutch, excel and brake pedals), a manual transmission and a virtual driving simulation. For the real vibration like situation on the road, six degree of freedom motion base system was used. Measured muscles were rectus femoris (RF), biceps femoris (BF), tibialis anterior (TA) and gastrocnemius (Gn) muscles. For the quantitative muscular activities, integrated electromyography (IEMG) was analyzed. Muscular fatigues also were analyzed through the analysis of the median frequency. In addition, foot pressures were analyzed and compared through the peak and averaged pressure during the operating three developed electronic pedals. The experiments are conducted with total 17 drivers, 11 general public and 6 drivers. As a result of the analysis, electromyogram and fatigue analysis through intermediate frequency reduction for pedal-1 more efficient than other pedals. And foot pressure also was decreased. Consequently, we suggested the most efficient pedal and method to minimize the amount of cumulative fatigue.