• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.1109-1112
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• 1999

본 논문에서는 영상확대 chip의 video 입력부에 부분화면을 저장할 frame memory의 구조를 개선하고자 하였다. 영상확대 video scaler인 gm833×2는 입력단 측에 frame buffer memory가 필요하게 되지만, 이를 외부에 장착하려면 일반적으로 대용량의 FIFO 메모리를 사용하게 된다. 이것은 dualport SRAM으로 구성이 되며, 메모리 제어를 고가의 FIFO칩에 의존하는 결과를 가져온다. 또한 기존의 scaler chip은 단순히 확대처리만을 하며, 입력 전, 후에 data의 변경 또는 이미지처리가 불가능한 구조가 된다. 본 논문에서는 외부에 필요한 메모리를 내장한 새로운 기능의 chip을 설계하는 데에 있어 필수적인 메모리제어 로직을 제안하고자 한다. 여기서는 더 나은 기능의 향상된 메모리 제어회로를 제시하고 이를 One-chip에 집적할 수 있도록 하였다 이를 사용한 Video Scaler Processor chip은 SDRAM을 별도의 제어회로 없이 외부에 장착할 수 있도록 하여 scaler의 기능을 향상시키면서 전체 시스템의 구조를 간단히 할 수 있을 것으로 기대된다. 본 논문에서는 먼저 메모리 제어회로를 포함한 Video Scaler Processor chip의 메모리제어 하드웨어의 구조를 제시하고, 메모리 access model과 제어로직을 소개하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• 전자공학회논문지 IE
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• v.47 no.3
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• pp.1-6
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• 2010

In this paper, it is designed a processor using embedded system so that moving picture can be expressed on LED electric sign board which has been expressed a simple message only like as a character or graphic. It has been fabricated a moving picture LED electric sign board which is composed to a video processor and LED display panel, in order to be able to express a digital moving picture of 24 bits that is transmitted from embedded system. It includes gamma adjustment, brightness, color contrast control, a schedule function, expression image conversion by the Internet and memory device. Also, an application program based Windows CE is designed so that a character, graphic, and moving picture can be expressed on a small LED electric sign board.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.6
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• pp.363-372
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• 2015

Recent some SoC FPGA Releases that integrate ARM processor and FPGA fabric show better performance compared to the ASIC SoC used in typical embedded image processing system. In this study, using the above advantages, we implement a SoC FPGA-based Real-Time Object Recognition and Tracking System. In our system, the video input and output, image preprocessing process, and background subtraction processing were implemented in FPGA logics. And the object recognition and tracking processes were implemented in ARM processor-based programs. Our system provides the processing performance of 5.3 fps for the SVGA video input. This is about 79 times faster processing power than software approach based on the Nios II Soft-core processor, and about 4 times faster than approach based the HPS processor. Consequently, if the object recognition and tracking system takes a design structure combined with the FPGA logic and HPS processor-based processes of recent SoC FPGA Releases, then the real-time processing is possible because the processing speed is improved than the system that be handled only by the software approach.

• The Transactions of the Korea Information Processing Society
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• v.5 no.8
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• pp.1972-1984
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• 1998

• Journal of Broadcast Engineering
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• v.20 no.5
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• pp.774-777
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• 2015

This paper introduces the world's first programmable video-processing platform for the enhancement of the video quality of the 8K(7680x4320) UHD(Ultra High Definition) TV operating up to 60 frames per second. In order to support required computing capacity and memory bandwidth, the proposed platform implemented several key features such as symmetric multi-cluster architecture for parallel data processing, a ring-data path between the clusters for data pipelining and hardware accelerators for computing filter operations. The proposed platform based on RP(Reconfigurable Processor) processes video quality enhancement algorithms and handles effectively new UHD broadcasting standards and display panels.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.1383-1386
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• 1997

Discrete cosine transform(DCT) is the most popular block transform coding in lossy mode. DCT is close to statistically optimal transform-the Karhunen Loeve transform. In this paper, a module for DCT encoder is made with TMS320C80 based on JPEG and MPEG, which are intermational standards for image compression. the DCT encoder consists of three parts-a transformer, a vector quantizer and an entropy encoder.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.585-588
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• 2004

This paper describes design and verification of the motion estimation and compensation unit using full search algorithm. Video processor is the key device of video communication systems. Motion estimation is the key module of video processor. The technologies of motion estimation and compensation unit are the core technologies for wireless video telecommunications system, portable multimedia systems. In this design, Verilog simulator and logic synthesis tools are used for hardware design and verification. In this paper, motion estimation and compensation unit are designed using FPGA, coded in Verilog HDL, and simulated and verified using Xilinx FPGA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.201-204
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• 2006

A system realization for real time DVR system with robust video watermarking algorithm against is attacked various is presented in this paper. The main system is composed of DSP processor and robust video watermarking to be processed at real time on image data and algorithm of the DVR system. The experimental result shows that the processing time takes about 2.5ms on the D1 size image per frame.