• Title/Summary/Keyword: Video Signal Generator

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Analysis of Signal Distortion for Ultra High Definition Video Pattern Control (UHD급 영상패턴 제어를 위한 전송선로의 신호 왜곡현상 분석)

  • Son, Hui-Bae;Jin, Jong-Ho;Rhee, Young-Chul
    • The Journal of the Korea institute of electronic communication sciences
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    • v.9 no.10
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    • pp.1197-1205
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    • 2014
  • Recently signal transmission of ultra high-definition(4K-UHD) video system is transferred as uncompressed high speed data. However, this has a limit to compose the system because EMI between separate cables of high speed interface section and skew bring distortion of the video signal and jitter. In this paper we applied V-by-One HS interface technique to transfer uncompressed high speed data. We analyzed HSD(High Speed Differential) transmission line signal integrity. Also we applied RF transmission technique instead of UHD video pattern control interface PCB design. When we measured V-by-One HS video signal of designed 4K-UHD class signal generator, We found that the transmission performance has been signal standard.

Driving System Design for Poly-Si TFT LCD of EWS (EWS급 Poly-Si TFT-LCD의 구동 시스템 설계)

  • Heon, Kwon-Byong;Park, Jong-Kwan;Cho, Kyu-Min;Choi, Myoung-Ryeul
    • Proceedings of the KIEE Conference
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    • 1999.07g
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    • pp.3120-3122
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    • 1999
  • In this paper we have designed the signal processing system for driving the Poly-Si TFT LCD of EWS. The signal processing system consist of timing controller, ramp signal generator and video signal processing system. Timing controller includes the top-down inversion. left right inversion, left-right shifting and control signal generator according to multi-source signal. The video signal processing system generates sawtooth-shaped waveform by using PROM and DAC for multi-gray scales and implements gamma correction function for compensating the TFT-LCD nonlinear charcteristic of the TFT-LCD. Finally we have discussed the experiment results and its application according to the designed TFT-LCD driving system.

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A Design of A Multistandard Digital Video Encoder using a Pipelined Architecture

  • Oh, Seung-Ho;Park, Han-Jun;Kwon, Sung-Woo;Lee, Moon-Key
    • Journal of Electrical Engineering and information Science
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    • v.2 no.5
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    • pp.9-16
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    • 1997
  • This paper describes the design of a multistandard video encoder. The proposed encoder accepts conventional NTSC/PAL video signals, It also processes he PAL-plus video signal which is now popular in Europe. The encoder consists of five major building functions which are letter-box converter, color space converter, digital filters, color modulator and timing generator. In order to support multistandard video signals, a programmable systolic architecture is adopted in designing various digital filters. Interpolation digital filters are also used to enhance signal-to-noise ratio of encoded video signals. The input to the encoder can be either YCbCr signal or RGB signal. The outputs re luminance(Y), chrominance(C), and composite video baseband(Y+C) signals. The architecture of the encoder is defined by using Matlab program and is modelled by using Veriflog-HDL language. The overall operation is verified by using various video signals, such as color bar patterns, ramp signals, and so on. The encoder contains 42K gates and is implemented by using 0.6um CMOS process.

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Analysis of Signal Integrity of High Speed Serial Interface for Ultra High Definition Video Pattern Control Signal Generator (UHD급 영상패턴 제어 신호발생기를 위한 고속 시리얼 인터페이스의 신호 무결성 분석)

  • Son, Hui-Bae;Kweon, Oh-Keun
    • Journal of Broadcast Engineering
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    • v.19 no.5
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    • pp.726-735
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    • 2014
  • In accordance with 4K UHD(Ultra High Definition) LCD television's higher resolution and data expansion, LCD TV had to face problems such as increasing numbers of cables and tangible skews problems among cables. The V-by-One HS is a new interface technology in the path between the image processing IC and timing control (TCON) board. The variable speed from 600 Mbps to 3.75 Gbps effectively meets the requirements of various different pixel rates. In this paper, we use the V-by-One HS interface to illustrate our proposed simulation method of frequency resonance mode and PCB design approach to model the effects of signal integrity for high speed video signal using an IBIS models.

Development of SDI Signal generator for Large size TFT-LCD (대형 TFT-LCD용 SDI 신호 생성기의 개발)

  • Choi, Dae-Seub;Sin, Ho-Chul
    • Journal of Satellite, Information and Communications
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    • v.9 no.1
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    • pp.13-16
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    • 2014
  • In applying LCD to TV application, one of the most significant factors to be improved is image sticking on the moving picture. LCD is different from CRT in the sense that it's continuous passive device, which holds images in entire frame period, while impulse type device generate image in very short time. To reduce image sticking problem related to hold type display mode, we made an experiment to drive TN-LCD like CRT. We made articulate images by fast refreshing images, and we realized the ratio of refresh time by counting between on time and off time for video signal input during 1 frame (16.7ms). Conventional driving signal cannot follow fast on-off speed, so we evaluated new signal generator using SDI (Serial Data Interface) mode signal generator. We realized articulate image generation similar to CRT by high fast full HD (High Definition) signals and TN-LCD overdriving. As a result, reduced image sticking phenomenon was validated by naked eye and response time measurement.

The Design and Characteristic Analysis of a Digital Signal Transmission System Based on Power Line Communications

  • Kim, Ji-Hyoung;Yun, Ji-Hun;Kim, Yong-K.;So, Byung-Moon
    • Transactions on Electrical and Electronic Materials
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    • v.10 no.6
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    • pp.222-226
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    • 2009
  • The objective of this study is to share multimedia contents included in existing digital devices and to solve the problems of an increase in installation fees and non-environmentally friendly interiors. This study designed a new digital signal transmitter and receiver using power line transmission and HDMI in order to solve the problems in the existing systems. The transmitter and receiver designed in this study used an AD9867BCPZ PLC chip in which the transmission came from digital signals originating in a PC, and the system architecture was configured so that the outputs signals were connected to a TV from the receiver. The experiment was implemented by adding a Video Test Generator, a USBPre external sound card, and Smaart Live 6 for analyzing the characteristics of the configured system. In the video test results, it was verified that communication was actively implemented, and the image quality showed a constant level from the measurement of the captured video. In the case of the sound, it was verified that more than 90% of the sound signals were normally transmitted and received from the examination of their phases and magnitudes. Thus, the performance of the system designed in this study was verified, which leads to the resolution of some of the problems found in current digital devices.

A Study on Signal Integrity of High Speed Interface for Ultra High Definition Video Pattern Control Signal Generator (초고해상도 영상패턴 제어 신호발생기의 고속 인터페이스 신호 무결성 실험에 관한 연구)

  • Son, Hui-Bae;Jun, June-Su;Kwon, Sai-Hoan
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2014.06a
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    • pp.150-152
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    • 2014
  • 디지털 평판 LCD TV의 영상신호 전송에 LVDS가 사용되어 왔으나 케이블간의 타이밍 문제가 대두되고 초고해상도의 컬러 Depth 확장으로 인해 보다 빠른 전송속도가 요구되어진다. V-by-One HS는 초고해상도 영상처리 IC 및 TCON 간의 새로운 인터페이스 기술로서 최대 3840*2160@240Hz의 해상도 영상구현이 가능하다. 동작 주파수 대역의 공진모드 전압 분포와 V-by-One HS IBIS(Input/Output Buffer Information Specification) 모델 시뮬레이션을 통하여 PCB 설계 방법을 제안한다. 본 논문에서는 V-by-One HS 인터페이스 기술을 사용하여 초고해상도 영상패턴 제어 신호발생기의 시스템 구성을 제안하고 고속영상 신호에 대한 신호 무결성을 검증하고자 한다.

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VLSI Architecture of General-purpose Memory Controller with High-Performance for Multiple Master (다중 마스터를 위한 고성능의 범용 메모리 제어기의 구조)

  • Choi, Hyun-Jun;Seo, Young-Ho;Kim, Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.1
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    • pp.175-182
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    • 2011
  • In this paper, we implemented a high-performence memory controller which can accommodate processing blocks(multiple masters) in SoC for video signal processing. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Selector, Mster Arbiter, Memory Signal Generator, Command Decoder, and memory Signal Generator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used. Since the designed H/W can be stably operated in 174.28MHz, it satisfies the specification of SDRAM technology.

Implementation of Personalized Advertisement and Information Application Services Using RFID Virtual Tag (RFID 가상 태그를 활용한 개인화된 광고 및 정보 응용 서비스 개발)

  • Park, Nam-Je
    • Journal of Information Technology Services
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    • v.8 no.4
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    • pp.151-163
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    • 2009
  • In this paper, we design and develop a personalized advertisement and information services system based on mobile RFID using RFID virtual tag. It is a system to perform the use of the contents information or the commercial transaction on the contents products through internet server connection by using RFID tag information with a mobile according as transmitting immediately to a cell phone after a tag generator derived RFID tag information to be substituted for the contents information being output at present, after being transmitted from a cell phone the information request signal on the contents information being output from video media. This service system provides a mechanism for gathering advertisement information left behind by many clients visiting advertisement sites for analysis of customers property, service model for selecting personalized services, and mechanism for providing them to customers who visited in a advertisement mall joined to the shopping site.

System Design of High-Definition Media Transceiver based on Power Line Communication and Its Performance Analysis (전력선 통신 기반 HD급 미디어 전송 시스템 설계 및 성능 분석)

  • Kim, Ji-Hyoung;Kim, Kwan-Woong;Kim, Yong-K.
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.1
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    • pp.192-196
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    • 2010
  • Due to a development of a modem technology as Power Line Communication(PLC) over 200 Mbps, the high-speed multi-media data trasmission could be currently possible. The strength of the PLC has no more additional wiring work. PLC has also possible to high quality data transmission with currently electrical cable. It has a various strong point campare with existing wire and wireless communication technologies. In This paper we develop a high quality media transmitter-receiver based on merging the HomePlug AV, which is 200 Mbps class PLC technology and HDMI Interface technology. The video function was used for the VEDEO TEST GENERATOR in order to a property valuation. Smart Live 6 software were used for the assessment of audio property. As the result of measurement of the HD class images by capturing from the receiver of the PLC, the quality of images couldn't be confirm any deterioration, which has compared with original reflections. In case of audio part as the result of confirmation of the Phase, Magnitude, it has been confirmed that over 90% of nomal transmition and receiving of acoustic signal. It can be possible to have HD class Media service through the PLC.