• Title/Summary/Keyword: Via Hole

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Interconnection Process and Electrical Properties of the Interconnection Joints for 3D Stack Package with $75{\mu}m$ Cu Via ($75{\mu}m$ Cu via가 형성된 3D 스택 패키지용 interconnection 공정 및 접합부의 전기적 특성)

  • Lee Kwang-Yong;Oh Teck-Su;Won Hye-Jin;Lee Jae-Ho;Oh Tae-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.12 no.2 s.35
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    • pp.111-119
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    • 2005
  • Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

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Application of Au-Sn Eutectic Bonding in Hermetic Rf MEMS Wafer Level Packaging (Au-Sn 공정 접합을 이용한 RF MEMS 소자의 Hermetic 웨이퍼 레벨 패키징)

  • Wang Qian;Kim Woonbae;Choa Sung-Hoon;Jung Kyudong;Hwang Junsik;Lee Moonchul;Moon Changyoul;Song Insang
    • Journal of the Microelectronics and Packaging Society
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    • v.12 no.3 s.36
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    • pp.197-205
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    • 2005
  • Development of the packaging is one of the critical issues for commercialization of the RF-MEMS devices. RF MEMS package should be designed to have small size, hermetic protection, good RF performance and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at the temperature below $300{\times}C$ is used. Au-Sn multilayer metallization with a square loop of $70{\mu}m$ in width is performed. The electrical feed-through is achieved by the vertical through-hole via filled with electroplated Cu. The size of the MEMS Package is $1mm\times1mm\times700{\mu}m$. By applying $O_2$ plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface as well as via hole. The shear strength and hermeticity of the package satisfy the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.

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Optimization of Laser Process Parameters for Realizing Optimal Via Holes for MEMS Devices (MEMS 소자의 비아 홀에 대한 레이저 공정변수의 최적화)

  • Park, Si-Beom;Lee, Chul-Jae;Kwon, Hui-June;Jun, Chan-Bong;Kang, Jung-Ho
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.34 no.11
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    • pp.1765-1771
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    • 2010
  • In the case of micro.electro-mechanical system (MEMS) devices, the quality of punched via hole is one of the most important factors governing the performance of the device. The common features that affect the laser micromachining of via holes drilled by using Nd:$YVO_4$ laser are described, and efficient optimization methods to measure them are presented. The analysis methods involving an orthogonal array, analysis of variance (ANOVA), and response surface optimization are employed to determine the main effects and to determine the optimal laser process parameters. The significant laser process parameters were identified and their effects on the quality of via holes were studied. Finally, an experiment in which the optimal levels of the laser process parameters were used was carried out to demonstrate the effectiveness of the optimization method.

Deep Learning Based TSV Hole TCD Measurement (딥러닝 기반의 TSV Hole TCD 계측 방법)

  • Jeong, Jun Hee;Gu, Chang Mo;Cho, Joong Hwee
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.2
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    • pp.103-108
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    • 2021
  • The TCD is used as one of the indicators for determining whether TSV Hole is defective. If the TCD is not normal size, it can lead to contamination of the CMP equipment or failure to connect the upper and lower chips. We propose a deep learning model for measuring the TCD. To verify the performance of the proposed model, we compared the prediction results of the proposed model for 2461 via holes with the CD-SEM measurement data and the prediction results of the existing model. Although the number of trainable parameters in the proposed model was about one two-thousandth of the existing model, the results were comparable. The experiment showed that the correlation between CD-SEM and the prediction results of the proposed model measured 98%, the mean absolute difference was 0.051um, the standard deviation of the absolute difference was 0.045um, and the maximum absolute difference was 0.299um on average.

Fuzzy-based Field-programmable Gate Array Implementation of a Power Quality Enhancement Strategy for ac-ac Converters

  • Radhakrishnan, N.;Ramaswamy, M.
    • Journal of Electrical Engineering and Technology
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    • v.6 no.2
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    • pp.233-238
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    • 2011
  • In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

Fbrication of tapered Via hole on Si wafer for non-defect Cu filling (결함없는 구리 충진을 위한 경사벽을 갖는 Via 홀 형성 연구)

  • Kim, In-Rak;Lee, Yeong-Gon;Lee, Wang-Gu;Jeong, Jae-Pil
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2009.05a
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    • pp.239-241
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    • 2009
  • DRIE(Deep Ion Reactive Etching) 공정은 실리콘 웨이퍼를 식각하는 기술로서 Si wafer 비아 홀 제조에 주로 사용되고 있다. 즉, DRIE 공정은 식각 및 보호층 증착을 반복함으로써 직진성 식각을 가능하게 하는 공정이다. 또한, 3차원 적층 실장에서 Si wafer 비아 홀에 결함없이 효과적으로 구리 충진을 하기 위해서는 직각형 via보다 경사벽을 가진 via가 형상적으로 유리하다. 본 연구에서는 3차원 적층을 위한 Si wafer 비아 홀의 결함 없는 효과적인 구리 충진을 위해, DRIE 공정을 이용하여 기존의 경사벽을 가지는 via 흘 형성 공정보다 더욱 효과적인 공정을 개발하였다.

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Copper Plating for Via Filling (비아홀 메움 동도금 기술)

  • Kim, Yu-Sang;Jeong, Gwang-Mi
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2015.05a
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    • pp.136-136
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    • 2015
  • 2007년 일본에서 지갑전화나 지상파 디지털TV 방송기능을 탑재한 휴대전화개발에 힘을 쏟고 있을 무렵, 해외에서 컴퓨터에 가까운 스마트폰이라는 다기능단말기 개발이 진행되고 있었다. 스마트폰은 젊은이를 중심으로 인기가 높아지고 있다. 휴대전화를 시작으로 정밀전자기기에는 인쇄배선판(이하, PWB: Printed Wiring Board)이 내장되어 있다. PWB는 향후 하이브리드차나 전기자동차의 발전과 함께, 차량탑재 수요도 높아질 것이다. 본고에서는 PWB를 지탱하는 동 도금 Via Hole메움에 대하여 기술하였다.

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Solution-Processed Quantum-Dots Light-Emitting Diodes with PVK/PANI:PSS/PEDOT:PSS Hole Transport Layers

  • Park, Young Ran;Shin, Koo;Hong, Young Joon
    • Proceedings of the Korean Vacuum Society Conference
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    • 2015.08a
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    • pp.146-146
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    • 2015
  • We report the enhanced performance of poly(N-vinylcarbozole) (PVK)/poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS)-based quantum-dot light-emitting diodes by inserting the polyaniline:poly (p-styrenesulfonic acid) (PANI:PSS) interlayer. The QD-LED with PANI:PSS interlayer exhibited a higher luminance and luminous current efficiency than that without PANI:PSS. Ultraviolet photoelectron spectroscopy results exhibited different electronic energy alignments of QD-LEDs with/without the PANI:PSS interlayer. By inserting the PANI:PSS interlayer, the hole-injection barrier at the QD layer/PVK interface was reduced from 1.45 to 1.23 eV via the energy level down-shift of the PVK layer. The reduced barrier height alleviated the interface carrier charging responsible for the deterioration of the current and luminance efficiency. This suggests that the insertion of PANI:PSS interlayer in QD-LEDs contributed to (i) increase the p-type conductivity and (ii) reduce the hole barrier height of QDs/PVK, which are critical factors leading to improve the efficiency of QD-LEDs.

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SPHERICAL WIND ACCRETION ONTO SUPERMASSIVE BLACK HOLE (우리은하 중심의 초거대 질량 블랙홀에 대한 구형 항성풍 부착)

  • Im, Su-Yeon;Park, Myeong-Gu
    • Publications of The Korean Astronomical Society
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    • v.10 no.1
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    • pp.79-90
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    • 1995
  • The unique compact radio source, Sgr $A^*$, at the Galactic center show many observational signs that it is powered by supermassive black hole. Recent observations also imply that it is surrounded by winds from nearby IR sources. So we explore the model in which multiwavelength spectrum from Sgr $A^*$ is due to the spherical accretion of these winds onto the central supermassive black hole. Improving upon the previous work, we allowed the possibility that ions and electrons have different temperatures, included the Compton effects and pair processes. Electrons radiate via cyclosynchrotron and bresstrahlung with comptoniztion. We find that ion approaches the virial temperature ${\sim}10^{13}K$ while electron temperature saturates at ${\sim}10^{10}K$. However, decoupling between ion and electron does not greatly affect the shape of the emission spectrum. When the mass of the black hole is ${\sim}10^6M_{\odot}$, radio, IR, X-ray, $\gamma$-ray band spectrum is reasonably explained by the model. Yet Compton effect which is neglected in previous works produces significant emission in IR band, which is marginally compatible with observations. Pair production is negligible and annihilation lines cannot be observed.

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Charge Carrier Photogeneration and Hole Transport Properties of Blends of a $\pi$-Conjugated Polymer and an Organic-Inorganic Hybrid Material

  • Han, Jung-Wook;An, Jong-Deok;Jana, R.N.;Jung, Kyung-Na;Do, Jung-Hwan;Pyo, Seung-Moon;Im, Chan
    • Macromolecular Research
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    • v.17 no.11
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    • pp.894-900
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    • 2009
  • This study examined the charge carrier photogeneration and hole transport properties of blends of poly (9-vinylcarbazole) (PVK), $\pi$-conjugated polymer, with different weight proportions (0~29.4 wt%) of (PEA)$VOPO_4{\cdot}H_2O$ (PEA: phenethylammonium cation), a novel organic-inorganic hybrid material, using IR, UV-Vis, and energy dispersive spectroscopy (EDS), thermogravimetric analysis (TGA), steady state photocurrent (SSPC) measurement, and atomic force microscopy (AFM). The SSPC measurements showed that the photocurrent of PVK was reduced by approximately three orders of magnitude by the incorporation of a small amount (~12.5 wt%) of (PEA) $VOPO_4{\cdot}H_2O$, suggesting that hole transport occurred through the PVK carbazole groups, whereas a reverse trend was observed at high proportions (>12.5 wt%) of (PEA)$VOPO_4{\cdot}H_2O$, suggesting that transport occurred via (PEA)$VOPO_4{\cdot}H_2O$ molecules. The transition to a trap-controlled hopping mechanism was explained by the difference in ionization potential and electron affinity of the two compounds as well as the formation of charge percolation threshold pathways.