• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.920-926
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• 2008

In this paper, small epsilon negative(ENG) zeroth-order resonance(ZOR) antenna with improved bandwidth is presented. To reduce the size of ENG ZOR antenna without narrowing bandwidth, large shunt inductance is introduced by adding patterns on patch and meandered via. The effective permittivity of meandered via is less dependent of frequency than that of straight via in same size. Thus, ENG ZOR antenna with meandered via has broader bandwidth. As a result, the bandwidth of ENG ZOR antenna with meandered via is 1.38 times as broad as that of spiral ENG ZOR antenna with straight via. On the other hand, the area of ENG ZOR antenna is reduced by 64 % compared with that of conventional mushroom ZOR antenna.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.16-22
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• 1993

A via-hole process for reproducible and reliable GaAs MMIC fabrication is described. The via-hole etching process consists of two step dry etching. During the first etching step a BC $I_{3}$/C $I_{2}$/Ar gas mixure is used to achieve high etch rate and small lateral etching. In the second etching step. CC $L_{2}$ $F_{2}$ gas is used to achieve selective etching of the GaAs substrate with respect to the front side metal layer. Via holes are formed from the backside of a 100$\mu$m thick GaAs substrate that has been evaporated initially with 500.angs. thick chromium and subsequently a 2000.angs. thick gold layer. The fabricated via holes are electroplated with gold (~20$\mu$m thick) to form via connections. The results show that established via-hole process is satisfactory for GaAs MMIC fabrication.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.859-861
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• 2001

VIA는 클러스터 또는 시스템 영역 네트워크를 위한 표준화된 사용자수준 통신 아키텍쳐이고, GFS는 LINUX 클러스터에서 사용할 수 있는 공유 락일 시스템이다. 클러스터 환경에서 GFS를 사용할 때 특별한 스토리지 네트워크가 설치되어 있지 않으면 GNBD를 사용한다. GNBD는 TCP/TP 상의 소켓을 기반으로 구현되어 있기 때문에, VIA를 사용하는 클러스터이더라도 VIA 하드웨어 상에서 TCP/IP 소켓을 통하여 GNBD를 작동시킨다. VIA와 같이 물리적 연결이 신뢰성이 높고 높은 수준의 기능을 제공하는 경우는 같은 클러스터 안에서 TCP/IP 프로토콜 스택을 사용할 필요가 없다. 본 논문은 VIA상에서 GNBD를 위한 고속 통신 계층(VCONN)을 제안하여, 동일한 VIA 하드웨어에서 지원되는 TCP/IP 모듈을 사용했을 때보다 읽기, 쓰기 성능을 각각 약 22%, 30% 향상시키는 방법을 소개한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.45-52
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• 2005

This paper presents the characterization of through hole vias on printed circuit board (PCB) through the time domain and frequency domain measurements. The time domain measurement was performed on a single via using the TDR, and the model parameters were extracted by the fitting simulation using HSPICE. The frequency domain measurement was also performed by using 2 port VNA, and the model parameters were extracted by fitting simulation with ADS. Using the ABCD matrices, the do-embedding equations were derived probing in the same plane in the VNA measurement. Based on the single via characterization, the differential via characterization was also performed by using TDR measurements. The time domain measurements were performed by using the odd mode and even mode sources in TDR module, and the Parameter values were extracted by fitting with HSPICE. Comparing measurements with simulations, the maximum calculated differences were $14\%$ for single vias and $17\%$ for differential vias.

• Asian Pacific Journal of Cancer Prevention
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• v.17 no.9
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• pp.4313-4318
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• 2016

Background: This study documented the performance of providers of visual inspection with acetic acid (VIA) at primary health centers, assessing their compliance with the VIA skills checklist and determinants of non-compliance, and exploring their perceptions of VIA training sessions. Materials and Methods: A cross-sectional study was conducted among VIA providers in the $Mekn\grave{e}s$-Tafilalet region of Morocco. Structured observation of their performance was conducted through supervisory visits and multiple focus group discussions (FGDs). Results: Performance of all the recommended steps for effective communication was observed in a low proportion of procedures (36.4%). Midwives/nurses had higher compliance than general practitioners (GPs) (p<0.001). All recommended steps for VIA examination were performed for a high proportion of procedures (82.5%). Compliance was higher among midwives/nurses than among GPs (p<0.001) and among providers in rural areas than those in urban areas (p<0.001). For pre-VIA counselling, all recommended steps were performed for only 36.8% of procedures. For post-VIA counseling, all recommended steps were performed in a high proportion (85.5% for VIA-negative and 85.1% for VIA-positive women). Midwives/nurses had higher compliance than GPs when advising VIA-positive women (p=0.009). All infection prevention practices were followed for only 14.2% of procedures, and compliance was higher among providers in rural areas than those in urban areas (p<0.001). Most FGD participants were satisfied with the content of VIA training sessions. However, they suggested periodic refresher training and supportive supervision. Conclusions: Quality assurance of a cervical cancer screening program is a key element to ensure that the providers perform VIA correctly and confidently.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.129-134
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• 2005

Electroplating copper is the important role in formation of 3D stacking interconnection in SiP (System in Package). The I-V characteristics curves are investigated at different electrolyte conditions. Inhibitor and accelerator are used simultaneously to investigate the effects of additives. Three different sizes of via are tested. All via were prepared with RIE (reactive ion etching) method. Via's diameter are 50, 75, $100{\mu}m$ and the height is $100{\mu}m$. Inside via, Ta was deposited for diffusion barrier and Cu was deposited fer seed layer using magnetron sputtering method. DC, pulse and pulse revere current are used in this study. With DC, via cannot be filled without defects. Pulse plating can improve the filling patterns however it cannot completely filled copper without defects. Via was filled completely without defects using pulse-reverse electroplating method.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.10
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• pp.539-549
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• 2002

PC cluster-based Information Retrieval (IR) systems improve their performances by parallel processing of query terms using cluster nodes. However TCP/IP based communication used to exchange data between cluster nodes prevents the performance from being improved further. The user-level communication mechanisms solve the problem by eliminating the time-consuming kernel access in exchanging data between cluster nodes. The Virtual Interface Architecture (VIA) is one of the representative user-level communication mechanisms which provide low latency and high bandwidth. In this paper, we propose a VIA-based parallel IR system on a PC cluster. The IR system is implemented using the following three communication methods: Sealable Coherent Interface (SCI) based VIA, MPI on SCI based VIA, MPI on Fast Ethernet based VIA. Through experiments, the performances of the three methods are analyzed in various aspects.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.65-74
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• 2013

The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.101-101
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• 2003

Al 박막의 화학증착(CVD)과 Al-Cu 합금박막의 물리증착(PVD)을 조합하는 CVD-PVD Al 공정은 수평방향의 배선과 수직방향의 via를 동시에 형성할 수 있으므로 공정단순화 및 생산원가절감 측면에서 장점이 있어서 DRAM 둥의 반도체 소자의 배선공정으로 매우 유망하다[1]. 본 연구에서는 CVD-PVD Al 공정을 이용하여 초고집적소자의 Al via와 Al 배선을 동시에 형성할 때 층간절연막의 영향을 조사하고 그 원인을 규명하였다. Al CVD를 위한 원료기체로는 dimethylaluminum hydride [($CH_3$)$_2$AlH]를 사용하였고 PVD는 38$0^{\circ}C$에서 실시하였다 층간절연막에 따른 CVD-PVD Al의 via hole 매립특성을 조사한 결과, high-density plasma(HDP) CVD oxide의 경우에는 via hole 매립특성이 우수하였으나, hydrogen silscsquioxane (HSQ)의 경우에는 매립특성이 우수하지 않아서 via 저항이 불균일 하였다. 이는 via 식각 후 wet cleaning 과정에서 HSQ에 흡수된 수분이 lamp를 이용한 degassing 공정에 의해서 완전히 제거되지 않아 CVD-PVD 공정 중에 탈착되어 Al reflow에 나쁜 영향을 미치기 때문으로 판단된다. CVD-PVD 공정 전에 40$0^{\circ}C$, $N_2$ 분위기에서 baking하여 HSQ 내의 수분을 충분히 제거함으로써 via 매립특성을 향상시킬 수 있었다. CVD-PVD Al 공정은 aspect ratio 10:1 이상의 via hole도 완벽하게 매립할 수 있었고 이에의해 제조된 Al 배선은 기존의 W plug 공정에 의해 제조된 배선에 비해 낮은 via 저항을 나타내었다.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.