• Title/Summary/Keyword: Via

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Laser Drilling System for Fabrication of Micro via Hole of PCB (인쇄회로기판의 미세 신호 연결 홀 형성을 위한 레이저 드릴링 시스템)

  • Cho, Kwang-Woo;Park, Hong-Jin
    • Journal of the Korean Society for Precision Engineering
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    • v.27 no.10
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    • pp.14-22
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    • 2010
  • The most costly and time-consuming process in the fabrication of today's multi-layer circuit board is drilling interconnection holes between adjacent layers and via holes within a layer. Decreasing size of via holes being demanded and growing number of via holes per panel increase drilling costs. Component density and electronic functionality of today's multi-layer circuit boards can be improved with the introduction of cost-effective, variable depth laser drilled blind micro via holes, and interconnection holes. Laser technology is being quickly adopted into the circuit board industry but can be accelerated with the introduction of a true production laser drilling system. In order to get optimized condition for drilling to FPCB (Flexible Printed Circuit Board), we use various drill pattern as drill step. For productivity, we investigate drill path optimization method. And for the precise drilling the thermal drift of scanner and temperature change of scan system are tested.

An Efficient high-speed reverse conversion method of the SIMD base for the decoder of the H.264 (H.264의 복호화기를 위한 SIMD기반의 효율적인 고속 역 변환 방법)

  • Yu Sang-Jun;Kim Seong-Hoon;Oh Seoung-Jun;Sohn Chae-Bong;Ahn Chang-Beom;Park Ho-Chong
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2004.11a
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    • pp.99-102
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    • 2004
  • 본 논문에서는 SIMD 명령어를 이용하여 H.264 복호화기의 역 정수 변환 과정과 역 양자화 과정을 고속으로 처리 할 수 있는 방법을 제안한다. 제안하는 고속 역 변환 방법을 ZERO 블록에 대하여 역 변환과 역 양자화 과정을 수행하지 않음으로써 속도 향상을 얻을 수 있다. 움직임이 적은 Akiyo 영상에서는 QP=0일 때 참조 코드(reference code)의 역 정수 변환과 역 양자화 과정에 비하여 7.52배, QP=24인 경우 8.1배의 속도 향상을 얻을 수 있다. 또한 움직임이 많은 Stefan 영상에 대해서는 QP=0일 때 고속 역 변환 방법이 참조 코드의 역 정수 변환과 역 양자화 과정에 비하여 6.7배. QP=36인 경우 7.83배의 속도 향상을 얻을 수 있다

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Study of Via-Typed Air-Gap for Logic Devices Applications below 45 nm Node

  • Kim, Sang-Yong;Kim, Il-Soo;Jeong, Woo-Yang
    • Transactions on Electrical and Electronic Materials
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    • v.12 no.4
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    • pp.131-134
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    • 2011
  • Back-end-of-line using ultra low-k (ULK; k < 2.5) has been required to reduce resistive capacitance beyond 45 nmtechnologies, because micro-processing units need higher speed and density. There are two strategies to manufacture ULK inter-layer dielectric (ILD) materials using an air-gap (k = 1). The former ULK and calcinations of ILD degrade the mechanical strength and induce a high cost due to the complication of following process, such as chemical mechanical polishing and deposition of the barrier metal. In contrast, the air-gap based low-k ILD with a relatively higher density has been researched on the trench-type with activity, but it has limited application to high density devices due to its high air-gap into the next metal layer. The height of air-gap into the next metal layer was reduced by changing to the via-typed air-gap, up to about 50% compared to that of the trench-typed air-gap. The controllable ULK was easily fabricated using the via-typed air-gap. It is thought that the via-type air-gap made the better design margin like via-patterning in the area with the dense and narrow lines.

Study on Via hole formation in multi layer MCM-D substrate using photosensitive BCB (감광성 BCB를 사용한 다층 MCM-D 기판에서 비아홀 형성에 관한 연구)

  • 주철원;최효상;안용호;정동철;김정훈;한병성
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.99-102
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    • 2000
  • Via for achieving reliable fabrication of MCM-D substrate was formed on the photosensitive BCB layer. MCM-D substrate consists of photosensitive BCB(Benzocyclobutene) interlayer dielectric and copper conductors. In order to form the vias in photosensitive BCB layer, the process of BCB and plasme etch using $C_2$F$_{6}$ gas were evaluated. The thickness of BCB after soft bake was shrunk down to 60% of the original. AES analysis was done on two vias, one is etched in $C_2$F$_{6}$ gas and the other is non etched. On via etched in $C_2$F$_{6}$, native C was detected and the amount of native C was reduced after Ar sputter. On via non etched in $C_2$F$_{6}$, organic C was detected and amount of organic C was reduced a little after Ar sputter. As a result of AES, BCB residue was not removed by Ar sputter, so plasma etch is necessary for achieving reliable via.ble via.

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Analysis of LED Package Properties by PCB Material and Via-hole Construction (PCB 재질 및 Via hole 구성에 따른 LED 패키지의 특성 분석)

  • Lee, Se-Il;Yang, Jong-Kyung;Kim, Sung-Hyun;Lee, Seung-Min;Park, Dae-Hee
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.11
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    • pp.2038-2042
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    • 2010
  • In this paper, we confirmed the thermal & optical properties for improving the heat transfer coefficient by changing the via hole size and in FR4 PCB with the same area. Osram 1W power LED Package (Golden Dragon) was used and the K-factor which is relative constant between LED junction temperature and forward bias was measured with power source meter(KEITHLEY 2430) to measure the thermal resistance from PCB configuration. As results, thermal resistance in metal PCB came out to the lowest as $26 [^{\circ}C/W]$ and thermal resistance in FR4 PCB without via-holes emerged as the highest as $69 [^{\circ}C/W]$. However thermal resistance of FR4 PCB could have decreased until $32[^{\circ}C/W]$ in 0.6 mm by using the via hole. Also, the luminous flux could have improved, too.

Electromigration Characteristics Stduy DCV Interconnect Structures in Cu Dual-Damascene Process (Cu Dual Damascene 배선 공정에서의 DCV 배선구조의 EM 특성 연구)

  • Lee, Hyun-Ki;Choi, Min-Ho;Kim, Nam-Hoon;Kim, Sang-Yong;Chang, Eui-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.123-124
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    • 2005
  • We investigated the effect of a Ta/TaN Cu diffusion barrier existence on the reliability and the electrical performance of Cu dual-damascene interconnects. A high EM performance in Cu dual-damascene structure was observed the BCV(barrier contact via) interconnect structure to remain Ta/TaN barrier layer. Via resistance was decreased DCV interconnect structure by bottomless process. This structure considers that DCV interconnect structure has lower activation energy and higher current density than BCV interconnect structure. The EM failures by BCV via structure were formed at via hole, but DCV via structure was formed EM fail at the D2 line. In order to improve the EM characteristic of DCV interconnect structure by bottomless process, after Ta/TaN diffusion barrier layer in via bottom is removed by Ar+ resputtering process, it is desirable that Ta thickness is thickly made by Ta flash process.

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Ring Hybrid Coupler using Microstrip Line with Via Transition (비아 트랜지션을 갖는 마이크로스트립 선로를 이용한 링 하이브리드 결합기)

  • Kim, Young;Sim, Seok-Hyun;Yoon, Young-Chul
    • Journal of Advanced Navigation Technology
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    • v.17 no.6
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    • pp.658-663
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    • 2013
  • In this paper, a microstrip line implementation using via transition and its application of multilayer compact ring hybrid coupler are presented. This transition is the sandwich structure with via hole to connect two microstrip lines in different layer. For designing a compact RF/Microwave passive circuit, the microstrip line using via-hole transition is proposed to reduce a size of microwave circuit with long transmission line. For the validation of the microstrip line with via-hole transition, the multilayer ring hybrid coupler is implemented at center frequency of 2 GHz. The measured performances are in good agreement with simulation results and about 50% size reduction compare to conventional ring hybrid coupler.

The Effects of Perceived Risks on Food Purchase Intention: The Case Study of Online Shopping Channels during Covid-19 Pandemic in Vietnam

  • NGUYEN, Cuong;TRAN, Doan;NGUYEN, Anh;NGUYEN, Nhan
    • Journal of Distribution Science
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    • v.19 no.9
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    • pp.19-27
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    • 2021
  • Purpose: Purchasing food via online shopping channels is booming during Covid-19 Pandemic in Vietnam. However, the perceived risks of food bought via online shopping channels may discourage consumers. Hence, this study assesses the effects of perceived risks on food purchase intention via online shopping channels in Vietnam. Research design, data and methodology: This study applied the multiple regression analysis with 253 samples collected from consumers who frequently purchase food via online shopping channels in Vietnam. The questionnaire is provided to respondents via Google Form. The sample collection method is convenience sampling. Three hundred samples were collected, but 253 samples are used after filtering the responses with missing data. The Exploratory Factor Analysis (EFA) and regression analysis are used for data analysis on SPSS software version 20. Results: The results show that product risk, security risk, time risk, and fraud risk of the seller negatively affect the intention to buy food via online shopping channels in Vietnam. Conclusions: The study provides several implications and recommendations for food companies and online food sellers. Reducing customers' perceived risks online food makes customers more willing to buy food online during Covid-19 Pandemic. Limitations and suggestions for further research are also discussed.

ED COB Package Using Aluminum Anodization (알루미늄 양극산화를 사용한 LED COB 패키지)

  • Kim, Moonjung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.10
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    • pp.4757-4761
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    • 2012
  • LED chip on board(COB) package has been fabricated using aluminum substrate and aluminum anodization process. An alumina layer, used as a dielectric in COB substrate, is produced on aluminum substrate by selective anodization process. Also, selective anodization process makes it possible to construct a thermal via with a fully-filled via hole. Two types of the COB package are fabricated in order to analyze the effects of their substrate types on thermal resistivity and luminous efficiency. The aluminum substrate with the thermal via shows more improved measurement results compared with the alumina substrate. These results demonstrate that selective anodization process and thermal via can increase heat dissipation of COB package in this work. In addition, it is proved experimentally that these parameters also can be enhanced using efficient layout of multiple chip in the COB package.

Fabrication of Laminated Multi-layer Flexible Substrate with Cu/Sn Via (Cu/Sn 비아를 적용한 일괄적층 방법에 의한 다층연성기판의 제조)

  • Lee H. J.;Yu Jin
    • Journal of the Microelectronics and Packaging Society
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    • v.11 no.4 s.33
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    • pp.1-5
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    • 2004
  • A multi-layer flexible substrate is composed of copper(Cu)/polyimide that are known as good electrical conductivity, and low dielectric constant, respectively. In this study. conductor line of $5{\mu}m$-pitch was successfully fabricated without non-uniform pattern shape by electroplating copper and coating polyimide on patterned stainless steel. For multi-layer flexible substrate, via holes were drilled by UV laser and filled with electroplating copper and tin. And then, the PI layer with vias and conductor lines was stripped from stainless steel substrate. The PI layers were laminated at once with careful alignment between layers. Solid state reaction between tin and copper during lamination formed the intermetallic compounds of $Cu_6Sn_5$($\eta$-phase) and $Cu_3Sn$($\epsilon$-Phase) and achieved a complete inter-connection by vertically positioning the plugged via holes on via pad. The via formation process has several advantages; such as better electrical property and lower cost than V type via and paste via.

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