• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.119-126
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• 2012

H.264/AVC can use three transforms depending on types of residual data which are to be coded. H.264/AVC always executes $4{\times}4$ DCT transform. In $16{\times}16$ intra mode only, $4{\times}4$ Hadamard transform for luma DC coefficients and $2{\times}2$ Hadamard transform for chroma DC coefficients are performed additionally. Quantization is carried out to achieve further data compression after transform coding is completed. In this paper, the hardware implementation for DCT transform, Hadamard transform and quantization is studied. Especially, the proposed architecture adopting the pipeline technique can output a quantized result per clock cycle after 33-clock cycle latency. The proposed architecture is coded in Verilog-HDL and synthesized using Xilinx 7.1i ISE tool. The operating frequency is 106MHz at SPARTAN3S-1000. The designed IP can process maximum 33-frame at $1920{\times}1080$ HD resolution.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.778-784
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• 2012

A symmetric block cryptosystem uses an identical cryptographic key at encryption and decryption processes. HIGHT cipher algorithm is 64-bit block cryptographic technology for mobile device that was authorized as international standard by ISO/IEC on 2010. In this paper, block cipher HIGHT algorithm is designed using Verilog-HDL. Four modes of operation for block cipher such as ECB, CBC, OFB and CTR are supported. When continuous message blocks of fixed size are encrypted or decrypted, the desigend HIGHT core can process a 64-bit message block in every 34-clock cycle. The cryptographic processor designed in this paper operates at 144MHz on vertex chip of Xilinx, Inc. and the maximum throughput is 271Mbps. The designed cryptographic processor is applicable to security module of the areas such as PDA, smart card, internet banking and satellite broadcasting.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.297-305
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• 2007

In the paper, a Motion JPEG2000 coder which has been set as the standard for image compression by the Digital Cinema Initiatives (DCI), an organization composed of major movie studios was implemented into a target FPGA. The DWT (Discrete Wavelet Transform) based on lifting and the Tier 1 of EBCOT (Embedded Block Coding with Optimized Truncation) which are major functional modules of the JPEG2000 were setup with dedicated hardware. The Tier 2 process was implemented in software. For digital cinema the tile-size was set to support $1024\times1024$ pixels. To ensure the real-time operations, three entropy encoders were used. When Verilog-HDL was used for hardware, resources of 32,470 LEs in Altera's Stratix EP1S80 were used, and the hardware worked stably at the frequency of 150Mhz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.61-66
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• 2008

Recently, portable devices which require small area and low power consumption employ applications using 3D graphics such as 3D games and 3D graphical user interfaces. We propose an efficient clipping engine algorithm which is suitable in 3D graphics pipeline. The clipping operation is divided into two steps: one is the selection process in the transformation engine and the other is the pixel clipping process in the scan conversion unit. The clipping operation is possible with addition of simple comparator. The clipping for the Y-axis is achieved in the edge walk stage and that for the X and Z-axis is performed in the span processing. The proposed clipping algorithm reduces the operation cycles and the area of of 3D graphics pipelines. We designed a 3D graphics pipeline with the proposed clipping algorithm using Verilog-HDL and verifies the operation using an FPGA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.85-92
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• 2009

This paper proposes a full-search block-matching motion estimation circuit with hybrid architecture combining systolic arrays and adder trees for an MPEG-4 encoder. The proposed circuit uses systolic arrays for motion estimation with a small number of clock cycles and adder trees to reduce required circuit resources. The interpolation circuit for 1/2 pixel motion estimation consists of six adders, four subtracters and ten registers. We improved the circuit performance by resource sharing and efficient scheduling techniques. We described the motion estimation circuit for integer and 1/2 pixels at RTL in Verilog HDL. The logic-level circuit synthesized by using 130nm standard cell library contains 218,257 gates and can process 94 D1($720{\times}480$) image frames per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.24-30
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• 2010

In this paper, we described intra prediction which is the one of techniques to be used for higher compression performance in H.264/AVC and proposed the design of intra predictor for efficient intra prediction mode processing. The proposed system is consist of processing elements, precomputation processing elements, an intra prediction controller, an internal memory and a register controller. The proposed system needs the reduced the computation cycles by using processing elements and precomputation processing element and also needs the reduced the number of access time to external memory by using internal memory and registers architecture. We designed the proposed system with Verilog-HDL and verified with suitable test vectors which are encoded YUV files. The proposed architecture belongs to the baseline profile of H.264/AVC decoder and is suitable for portable devices such as cellular phone with the size of $176{\times}144$. As a result of experiment, the performance of the proposed intra predictor is about 60% higher than that of the previous one.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.17-22
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• 2009

FlexRay is a new standard of network communication system which provides solutions to the degradation problems generated by many ECU (Electronic Control Unit) connections in automobiles and automation systems. The upper bound of the data rate is 10Mbps and it provides two channels for redundancy In this paper, FlexRay system is first designed using SDL. For hardware implementation, FlexRay system is designed using Verilog HDL based on the SDL design result. The designed system is synthesized using Synopsys Design Compiler with the Magna/Hynix 0.18 um cell library. In this paper, to construct a FlexRay network, active star is used since active star systems can provide high speed data transmission up to 10Mbps. The performance of the star network is tested using one transmitter node and two receiver nodes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.369-372
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• 2003

This paper describes a design of OFDM (Orthogoanl Frequency Division Multiplexing) based wireless LAN system receiver, defined in IEEE 802.11a standards. Because OFDM system uses several orthogonal sequence sets, it ran avoid selective fading of fast data transfer problem when it is used with error correction code. But if the receiver is not synchronized, the orthogonal of between sub-ralliers will be destroyed and the data interruption will be generated. So it makes error property get worse very murk. For improving the noise error, we use the relationship of phasor between sub-carriers and make system synchronization using one tab equalizer. The designed OFDM block is described by Verilog HDL for the efficient and small size hardware. And we preform the functional verification and evaluation using the vector of standards.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2380-2388
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• 2015

A hardware implementation of MOD(moving object detection) algorithm using EGML(effective Gaussian mixture learning)- based background subtraction to detect moving objects in video is described. Some approximations of EGML calculations are applied to reduce hardware complexity, and pipelining technique is adopted to improve operating speed. The MOD processor designed in Verilog-HDL has been verified by FPGA-in-the-loop verification using MATLAB/Simulink. The MOD processor has 2,218 slices on the Virtex5-XC5VSX95T FPGA device and its throughput is 102 MSamples/s at 102 MHz clock frequency. Evaluation results of the MOD processor for 12 images in the IEEE CDW-2012 dataset show that the average recall value is 0.7631, the average precision value is 0.7778 and the average F-measure value is 0.7535.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.673-676
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• 2008

In wireless communications such as Bluetooth, Baseband should be able to minimize the DC bias of the data which passed the modem interface of either transmitter or receiver for the reliability of the circuit and the integrity of the data. The transmitter scrambles the data to send randomly to the error correction block and the receiver recovers the randomly spread data as they have been. To design the whitening block, it is important to select the prime polynomial for the filtering. In this paper, we designed a optimal whitening block using the prime polynomial $g(D)=D^7+D^4+1$ for hardware and area efficiency. The proposed hardware whitening block was described and verified using Verilog HDL and later to be automatically synthesized. The synthesized whitening block operated at 40Mhz normal clock speed of the target baseband microcontroller.