• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2091-2097
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• 2007

This paper described the verification of modeling technique of underground distribution from comparison between field test and simulation. It needs more exact transient phenomenon analysis model to establish lightning protection of underground distribution line. Although, there were a lot of transient phenomenon researches, nobody could has verified the confidence of modeling from field tests in interior until now. So, simulation model verified field test is needed to analyse transient phenomenon of underground distribution system. The examination must be accomplished in many different condition before suggesting these verified analysis model. In this paper, the conditions were examined and the various data results on the different line composition was compared with the EMTP simulation, when the lightning impulse test was accomplished at underground distribution line. Also the value between field test and simulation was very closed and the method of modeling has demonstrated confidence, when the method is used to analyse domestic transient phenomenon of underground distribution.

• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2001.04a
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• pp.394-402
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• 2001

In order to lessen cable vibration, new cable damper system with high damping rubber was developed using the basis of the LRB design scheme. The analysis model of cable damper system incorporate voigt-kelvin damper model into the nonlinear cable analysis model. To achieve maximum damping capacity both reducing damper stiffness and developing high damping rubber were performed. As a result of verification test, the high damping rubber damper show its effectiveness in improving cable damping capacity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.5
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• pp.650-662
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• 1993

The thesis describes the realization and test of the transport layer operating on the CLNS (Connection Less Network Service) which is specified by ISO 8073 and ADDENDUM 2 protocol. For realization of the transport layer, five modules and interface primitives were definde. This protocol was formally described by SDL (Specification and Description Language) and was programmed in C-language. For verification of the software, protocol tester was implemented and test scenarios were defined. The verification was accomplished based on the test scenarios. Transport Layer software presented in this thesis may be utilized in a real situation with some modifications. Protocol tester presented in this thesis can also be used for verification of other protocol softwares.

• Journal of Broadcast Engineering
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• v.21 no.5
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• pp.792-802
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• 2016

Real time verification is necessary, since there are several features that cannot be verified through design simulation in the design of multiband soundbar system. And then this paper describes an implementation of an FPGA-based real-time verification system for a soundbar SoC with an embedded processor. It is verified a real-time performance test and a listening test which are several features in the design stage that cannot be verified through a design simulation. The measurement of quantitative specifications such as SNR, THD+N, frequency response, etc. as well as the listening test were performed through the implemented FPGA system, and it was verified that test results satisfied the target specifications.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.2
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• pp.153-161
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• 2011

Korea Aerospace Research Institute (KARI) has implemented an integrity monitor testbed (IMT) to provide archived GPS data and test results for integrity monitoring algorithm development. To verify that the system is implemented based on international standard requirements, this paper represents the basic functional verification test results of the implemented testbed as a GBAS reference station. It compares the IMT generated GBAS message fields with those of PEGASUS, which is a baseline toolset accepted by international GBAS experts, to show the validity of the correction information. It also verifies the integrity and availability of the system through analysis on GBAS user data in the range and position domain.

• Journal of Platform Technology
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• v.8 no.4
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• pp.47-58
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• 2020

DO-330 Software Tool Qualification Considerations is a guideline for development of tools used to develop/verify software and hardware installed on aircraft. And among several processes, the verification process is very crucial as it occupies a large proportion for DO-330. Especially, in order to qualify tool with high safety level, test objectives must be performed with independence, accordingly, more time, cost, and manpower are required than other objectives. In addition, even if the test cases or test procedures are well defined, the higher the complexity of the test the higher probability of human error occurs. In this paper, we propose Script-based Test Automation Agent software structure for efficient DO-330 verification process of A661UAGEN tool developed by Hanwha Systems. Compared to the test performed manually by the test engineer, testing time of the Script-based Test Automation Agent is reduced by 87.5% and testing productivity is increased by 43.75%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.24-30
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• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• Journal of the Korean Society of Industry Convergence
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• v.22 no.6
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• pp.689-702
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• 2019

This paper deals with the verification of the functions about mining robot, which is the system for developing deep seabed resources by applying V&V(verification and validation). In order to overcome water pressure of 500 bar and to travel on soft ground, and to operate in deep sea environment with bad conditions, it is necessary to develop a robot that can satisfy various deepsea conditions. A mining robot has been developed based on simulation based design and Multidisciplinary design optimization. In order to verify the developed robot, lab test and real sea test should be performed for various marine environment conditions. There are too many requirements to consider, such as space, time, cost, personnel, and environment to do performance test. So it is costly and time consuming for developing robot. In order to solve this problems, V&V technique was applied to mining robot. The stages of mining robot design, fabrication and commission were verified.

• Journal of the Korea Society of Computer and Information
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• v.26 no.9
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• pp.105-114
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• 2021

ESICD(Electrical Signal Interface Control Document) refers to a document that describes protocols and data for communication between components consist of a system. Each component developer gathers at a specific place to conduct an integrated test for ESICD verification. In this case, it often happens that the integration test is delayed due to a simple mistake of software developers. There are two reasons for this situation: First, software developers do not perform sufficient verification because it is difficult to configure the system environment in a Lab, and second, they do not immediately find the cause of errors occurred during integration tests. Therefore, in this paper, we propose a strategy to effectively perform ESICD verification, which takes a lot of time between the production and implementation stage of the weapon system development stage and the system integration test stage.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.325-328
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• 2001

This paper describes a VHDL code coverage checker for If design and verification. Applying the verification coverage to IP design is a methodology rapidly gaining popularity. This enables the designers to improve the IP design quality and reduces the time-to-market by providing the Quantitative measure of simulation completeness and test benches. To support this methodology, a VHDL code coverage model was defined and the measurement tool was developed.