• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.117-123
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• 2012

This paper implements mobile Worldwide Interoperability for Microwave Access (WiMAX) receiver using Software Defined Radio (SDR) technology. SDR system is difficult to implement on the mobile handset because of restrictions that are computing power and under space constraints. The implemented receiver processes mobile WiMAX software modem on Open Multimedia Application Platform (OMAP) System on Chip (SoC) and Field Programmable Gate Array (FPGA). OMAP SoC is composed of ARM processor and Digital Signal Processor (DSP). ARM processor supports Single Instruction Multiple Data (SIMD) instruction which could operate on a vector of data with a single instruction and DSP is powerful image and video accelerators. For this reason, we suggest the possibility of SDR technology in the mobile handset. In order to verify the performance of the mobile WiMAX receiver, we measure the software modem runtime respectively. The experimental results show that the proposed receiver is able to do real-time signal processing.

• 한국전산유체공학회:학술대회논문집
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• 2007.04a
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• pp.91-94
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• 2007

A GUI based pre/post processor program, which is based on the MFC and OpenGL library in the Windows O/S, hee been developed for NUFLEX Using this program, users are able to generate and modify structured or unstructured grid geometries, set all the parameters for the solver, and observe the results of the simulation in graphic view by vector or scalar plots. The mesh geometry data can be imported from or exported to other programs by supporting functions for reading from and writing to CGNS data format files.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.619-622
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• 1991

In this paper, a digitalization of Induction Motor Vector Control System is proposed, where all processings are executed by using a processor. In Vector Control System, where the motor voltages are controlled by using the motor voltage model, the variation of the rotor flux-interlinkage is very small however the deviation of the torque becomes large. Thus, in order to enhance the torque performance, voltage model based vector control scheme with minor current loops, which can eliminate the high frequency current harmonics is used.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1336-1345
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• 2016

A modified space vector pulse width modulation (SVPWM) strategy based on vector space decomposition and its equivalent carrier-based PWM realization are proposed in this paper, which is suitable for six-phase asymmetrical dual stator induction machines (DSIMs). A DSIM is composed of two sets of symmetrical three-phase stator windings spatially shifted by 30 electrical degrees and a squirrel-cage type rotor. The proposed SVPWM technique can reduce torque ripples and suppress the harmonic currents flowing in the stator windings. Above all, the equivalent relationship between the proposed SVPWM technique and the carrier-based PWM technique has been demonstrated, which allows for easy implementation by a digital signal processor (DSP). Simulation and experimental results, carried out separately on a simulation system and a 3.0 kW DSIM prototype test bench, are presented and discussed.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1203-1205
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• 2001

In this paper, the speed control system of induction motor was proposed using vector control algorithm and space voltage vector PWM method to improve the dynamic performance of induction motor. The control system is composed of the PDFF controller for speed control and the current controller using space voltage vector PWM technique. The high-speed calculation and processing for vector control is carried out by TMS320C31 digital signal processor and IPM. The proposed scheme is verified through digital simulations and experiments for 3.7(kw) induction motor and shows good dynamic performance.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.2
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• pp.1043-1056
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• 2017

A styled document is a document that contains diverse decorating functions such as different font, colors, tables and images generally authored in a word processor (e.g., MS-WORD, Open Office). Compared to a plain-text document, a styled document enables a human to easily recognize a logical structure such as section, subsection and contents of a document. However, it is difficult for a computer to recognize the structure if a writer does not explicitly specify a type of an element by using the styling functions of a word processor. It is one of the obstacles to enhance document version management systems because they currently manage the document with a file as a unit, not the document elements as a management unit. This paper proposes a machine learning based approach to analyzing the logical structure of a styled document composing of sections, subsections and contents. We first suggest a feature vector for characterizing document elements from a styled document, composing of eight features such as font size, indentation and period, each of which is a frequently discovered item in a styled document. Then, we trained machine learning classifiers such as Random Forest and Support Vector Machine using the suggested feature vector. The trained classifiers are used to automatically identify logical structure of a styled document. Our experiment obtained 92.78% of precision and 94.02% of recall for analyzing the logical structure of 50 styled documents.

• The Transactions of the Korea Information Processing Society
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• v.3 no.1
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• pp.167-180
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• 1996

In the scalar processing oriented machine scalar operations must be performed for the vector processing as many as the number of vector components. So called a vector processing mechanism by the von Neumann operational principle. Accessing vector data hasto beperformed by theevery pointing ofthe instruction or by the address calculation of the ALU, because there is only a program counter(PC) for the sequential counting of the instructions as a memory accessing device. It should be here proposed that an access unit dimensionally to address components has to be designed for the compensation of the organizational hardware defect of the conventional concept. The necessity for the vector structuring has to be implemented in the instruction set and be performed in the mid of the accessing data memory overlapped externally to the data processing unit at the same time.

• Journal of Korea Multimedia Society
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• v.11 no.10
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• pp.1460-1470
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• 2008

As the performance of recent mobile systems increases, a vector graphic has been implemented to represent various types of dynamic menus, mails, and two-dimensional maps. This paper proposes a hardware accelerator for open vector graphics (OpenVG), which is widely used for two-dimensional vector graphics. We analyze the specifications of an OpenVG and divide the OpenVG into several functions suitable for hardware implementation. The proposed hardware accelerator is implemented on a field programmable gate array (FPGA) board using hardware description language (HDL) and is about four times faster than an Alex processor.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.8
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• pp.445-455
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• 2002

In this paper, we present a new task scheduling scheme ior the efficient execution of the tasks of compound nodes of hierarchical task graph(HTG) on shared memory system. The proposed scheme for exploitation functional parallelism is autoscheduling that performs the role of scheduling by processor itself without any dedicated global scheduler. To adapt the proposed scheduling scheme for various platforms, Including a uni-processor systems, Java threads were used for implementation, and the performance is analyzed in comparison with a conventional bit vector method. The experimental results showed that the proposed method was found to be more efficient in its execution time and exhibited good load-balancing when using the experimental parameter values. Furthermore, the memory size could be reduced when using the proposed algorithm compared with a conventional scheme.

• Journal of Broadcast Engineering
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• v.10 no.1 s.26
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• pp.77-82
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• 2005

We propose a highly Integrated motion estimation processor (MEP) for efficient video compression in an SoC platform. When compressing video by the standards like MPEG-4 and H.263, the macroblock related functions motion compensation. mode decision, motion vector prediction, and motion vector difference calculation require the frequent intervention of MCU. Thus the proposed MEP incorporates those functions with the motion estimation capability to reduce the number of interrupts to MCU, which can lead to a highly efficient SoC system. For low-power consumption, the proposed MEP can prevent the temporally static area from motion estimation or can skip the half-pel motion estimation for those macroblocks whose modes are decided as INTRA.