• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.989-990
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• 2006

This paper presents a design of 3D Graphics Geometry processor. A geometry processor needs to cope with a large amount of computation and consists of transformation processor and lighting processor. To deal with the huge computation, a vector processing structure based on pipeline chaining is proposed. The proposed geometry processor performs 4.3M vertices/sec at 100MHz using 11 floating-point units.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.1977-1983
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• 1998

An algorithm-based fault tolerant scheme for the vector convolution is proposed employing the positive and negative checksum vectors that are defined in this paper based on the encoder vector. The proposed scheme is implemented on the aray processor, and then the amount of redundancy is examined thrugh the complexity analysis.

• Journal of Power Electronics
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• v.10 no.3
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• pp.277-284
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• 2010

This paper presents a novel hybrid carrier based space vector modulation for cascaded multilevel inverters. The proposed technique inherits the properties of carrier based space vector modulation and the fundamental frequency modulation strategy. The main characteristic of this modulation are the reduction of power loss, and improved harmonic performance. The carrier based space vector modulation algorithm is implemented with a TMS320F2407 digital signal processor. A Xilinx Complex Programmable Logic Device is used to develop the hybrid PWM control algorithm and it is integrated with a digital signal processor for hybrid carrier based space vector PWM generation. The inverter offers less weighted total harmonic distortion and it operates with equal electrostatic and electromagnetic stress among the power devices. The feasibility of the proposed technique is verified by spectral analysis, simulation, and experimental results.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.12
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• pp.723-731
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• 2005

The $4{\times}4$ homogeneous transformation matrix is a compact representation of orientation and position of an object in robotics and computer graphics. A coordinate transformation is accomplished through the successive multiplications of homogeneous matrices, each of which represents the orientation and position of each corresponding link. Thus, for real time control applications in robotics or animation in computer graphics, the fast multiplication of homogeneous matrices is quite demanding. In this paper, a parallel-architecture vector processor is designed for this purpose. The processor has several key features. For the accuracy of computation for real application, the operands of the processors are floating point numbers based on the IEEE Standard 754. For the parallelism and reduction of hardware redundancy, the processor takes column vectors of homogeneous matrices as multiplication unit. To further improve the throughput, the processor structure and its control is based on a pipe-lined structure. Since the designed processor can be used as a special purpose coprocessor in robotics and computer graphics, additionally to special matrix/matrix or matrix/vector multiplication, several other useful instructions for various transformation algorithms are included for wide application of the new design. The suggested instruction set will serve as standard in future processor design for Robotics and Computer Graphics. The design is verified using FPGA implementation. Also a comparative performance improvement of the proposed design is studied compared to a uni-processor approach for possibilities of its real time application.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.2
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• pp.87-93
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• 2013

In this paper, we implemented and evaluated the performance of a vector-based rasterization algorithm of 3D graphics using a SIMD-based many-core processor that consists of 4,096 processing elements. In addition, we compared the performance and efficiency of the rasterization algorithm using the many-core processor and commercial GPU (Graphics Processing Unit) system which consists of 7 GPUs and each of which have 512 cores. Experimental results showed that the SIMD-based many-core processor outperforms the commercial GPU system in terms of execution time (3.13x speedup), energy efficiency (17.5x better), and area efficiency (13.3x better). These results demonstrate that the SIMD-based many-core processor has potential as an embedded mobile processor.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.2
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• pp.44-50
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• 1993

In this paper, we will present an array processor for implementation of digital neural networks. Back-propagation model can be formulated as a consecutive matrix-vector multiplication problem with some prespecified thresholding operation. This operation procedure is suited for the design of an array processor, because it can be recursively and repeatedly executed. Systolic array circuit architecture with Residue Number System is suggested to realize the efficient arithmetic circuit for matrix-vector multiplication and compute sigmoid function. The proposed design method would expect to adopt for the application field of neural networks, because it can be realized to currently developed VLSI technology.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.273-276
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• 2002

In this paper, we propose a bias random vector generator which can verify functions of microprocessor effectively. This generator is a pre-processor of assembly program, and defines pre-processor instructions which create random vector only in the pall which the designer wants to verify. Therefore, this generator shows higher detection ration than any other generators. And, we can cut down design costs because of shortening a Period for verifying function.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.121-124
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• 2002

In this paper, we propose a bias random vector generator which can verify functions of microprocessor effectively. This generator is a pre-processor of assembly program, and defines pre-processor instructions which create random vector only in the part which the designer wants to verify. Therefore, this generator shows higher detection ration than any other generators. And, we can cut down design costs because of shortening a period for verifying function.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.837-840
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• 2005

This paper presents 3D graphics lighting processor based on vector processing using pipeline chaining. The lighting process of 3D graphics rendering contains many arithmetic operations and its complexity is very high. For high throughput, proposed processor uses pipelined functional units. To implement fully pipelined architecture, we have to use many functional units. Hence, the number of functional units is restricted. However, with the restricted number of pipelined functional units, the utilization of the units is reduced and a resource reservation problem is caused. To resolve these problems, the proposed architecture uses vector processing using pipeline chaining. Due to its pipeline chaining based architecture, it can perform 4.09M vertices per 1 second with 100MHz frequency. The proposed 3D graphics lighting processor is compatible with OpenGL ES API and the design is implemented and verified on FPGA.