• Proceedings of the KIEE Conference
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• 1992.07a
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• pp.245-247
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• 1992

We utilize as a processor TMS320C25 (Texas Instrument) in making a driver for a 4 pole PM synchronous servo motor. TMS320C25 has a 32bit ALU and a 16 bit hardware multiplier, and the maximum instruction execution rate is 10MIPS at 40MHz. We adopted a space vector modulation PWM method. An interesting point of this work is that PWM wave is generated by utilizing timer interrupts. Hence, in the rest of time the processor can take care of the other routine such as Park's coordinate transformation and the computation required in the feedback loops. Thus, it mates the hardware circuit very simple. Due to the decrease in the number of components, the motor drive system becomes more fault-tolerant and cost-optimized. Also, more flexibility is gained in changing the control parameters.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.867-870
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• 2003

본 논문은 멀티미디어 데이터 처리를 위한 효율적인 RISC 프로세서 유닛의 설계를 목표로 Vector 프로세서의 SIMD(Single Instruction Multiple Data) 개념을 바탕으로 고정된 연산기 데이터 비트 수에 비해 상대적으로 작은 비트수의 데이터 연산의 부분 병렬화를 통하여 멀티미디어 데이터 연산의 기본이 되는 곱셈누적(MAC : Multiply and Accumulate) 연산의 성능을 향상 시킨다. 또한 기존의 MMX나 VIS 등과 같은 범용 프로세서들의 부분 병렬화를 위해 전 처리 과정의 필요충분조건인 데이터의 연속성을 위해 서로 다른 길이의 데이터 흑은 비트 수가 작은 멀티미디어의 데이터를 하나의 데이터로 재처리 하는 재정렬 혹은 Packing/Unpacking 과정이 성능 전체적인 성능 저하에 작용하게 되므로 본 논문에서는 기존의 프로세서의 연산기 구조를 재이용하여 병렬 곱셈을 위한 연산기 구조를 구현하고 이를 위한 데이터 정렬 연산 구조를 제안한다.

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.94-100
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• 1999

This paper concerns the implementation of a digital neural network which performs the high speed operation of Hopfield model's arithmetic operation. It is also designed to use a look-up table and produce floating point arithmetic of nonlinear function with high speed operation. The arithmetic processing of Hopfleld is able to describe the matrix-vector operation, which is adaptable to design the array processor because of its recursive and iterative operation .The proposed method is expected to be applied to the field of real neural networks because of the realization of the current VLSI techniques.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.345-350
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• 1986

This paper deseribes the design of a vector-coordinate rotation processor and the apporoximate evaluations of sine and consine based upon the use of residue number systems. The proposed algorithm results in a considerable improvement of computational speed as compared to the CORDIC algorithm. According to the results of computer simulation, the mean error of sine and cosine is 0.0025, and the mean error of coorcinate rotation arithmatic is 0.65. The proposed processor has the efficiency for the design and fabrication of integrated circuits, because it consists of an array of identical lookup tables.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.6
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• pp.1011-1018
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• 2006

Due to rapid development of mobile communication terminals and various requests of their users, multimedia information including image information has been the basis of mobile communication contents. In order to use vectored image information efficiently, which is more favorable than bit-mapped image information when transmission delay time and costs are considered, efficient vector graphics supporting systems are needed. Therefore, vector graphics kernel systems have been proposed and standardization attempts have been made in order to increase interoperability. In this paper, a vector graphics kernel based on OpenVG is designed and implemented. OpenVG was proposed as a standard vector graphics kernel by Khronos Group recently. The implemented vector graphics kernel, named by alexVG, is developed on a PC emulator as well as on a development board equipped with an ARM processor. In addition, performance tests are made in order to verify its functions.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.1406-1409
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• 2004

The Resolver usually used in industry is the absolute angle analog sensor that must be in order to driving BLDC (brushless DC) motor, and it needs RDC(Resolver-to-Digital converter) for changing the output signal to digital to be applied to the SVPWM(Space Vector Pulse Width Modulation) algorithm. Commonly used S/W RDC needs trigonometric function. What it takes a lot of calculation time of processor is gotten at weak point. In this paper, S/W RDC is realized except trigonometric functions as a result of feedback resolver outputs after filtering using FIR filter. thus, processing time is reduced. So, One-chip DSP Controller operating the Vector Control, RDC, and SVPWM can be designed.

• Proceedings of the KIEE Conference
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• 2004.10a
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• pp.92-94
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• 2004

This paper presents modeling of dynamic system for slot less air-cored PM linear synchronous motor using space vector PWM. The vector control requires Information about rotor position. And we can need to the Hall sensor for sampling current. In order to agree with this purpose, Digital Signal Processor(TMS320F2406A) developed for implementation of a speed Field Oriented Control.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2748-2750
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• 1999

This Paper describes the design of an induction motor control using the TMS320C32 Digital Signal Processor and the ADMC201 motion coprocessor. Presented hardware architecture can be used for several industry applications with wide range of speed control, e.g. elevator and cranes application, servo motor, electrical vehicles. The main purpose of the paper is demonstration of the implementation and maximum utilization of the ADMC201 motion coprocessor in digital vector control system for AC drives.

• Proceedings of the KSME Conference
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• 2001.11b
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• pp.410-416
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• 2001

An algorithm of 3-D particle image velocimetry(3D-PIV) was developed for the measurement of 3-D velocity field of complex flows. The measurement system consists of two or three CCD camera and one RGB image grabber. In this study, stereo photogrammetty was applied for the 3-D matching of tracer particles. Epipolar line was used to decect the stereo pair. 3-D CFD data was used to estimate algorithm. 3-D position data of the first frame and the second frame was used to find velocity vector. Continuity equation was applied to extract error vector. The algorithm result involved error vecotor of about 0.13 %. In Pentium III 450MHz processor, the calculation time of cross-correlation for 1500 particles needed about 1 minute.

• Laser Solutions
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• v.2 no.3
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• pp.19-31
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• 1999

This paper introduces the monitoring scheme of laser welding quality using neural network. The developed monitoring scheme detects light signal emitting from plasma formed above the weld pool with optic sensor and DSP-based signal processor, and analyzes to give a guidance about the weld quality. It can automatically detect defects of laser weld and further give an information about what kind of defects it is, specially partial penetration and porosity among the interior defects. Those could be detected only by naked eyes or X-ray after welding, which needs more processes and costs in mass production. The monitoring scheme extracts four feature vectors from signal processing results of optical measuring data. In order to classify pattern for extracted feature vectors and to decide defects, it uses single-layer neural network with perceptron learning. The monitoring result using only the first feature vector shows confidence rate in recognition of 90%($\pm$5) and decides whether normal status or defects status in real time.