• Title/Summary/Keyword: Variable block sizes

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A Fast Sub-pixel Motion Estimation Algorithm Using Motion Characteristics of Variable Block Sizes (가변블록에서의 움직임 특성을 이용한 부화소 단위 고속 움직임 예측 방법)

  • Kim, Dae-Gon;Kim, Song-Ju;Yoo, Cheol-Jung;Chang, Ok-Bae
    • Proceedings of the Korean Information Science Society Conference
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    • 2007.06d
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    • pp.560-565
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    • 2007
  • 본 논문에서는 H.264 동영상 표준의 가변 움직임 블록을 위한 고속 움직임 예측 기법을 제안한다. 움직임 예측은 H.264의 비디오 코딩 과정에서 가장 많은 연산량을 차지하는 중요한 처리과정이다. 움직임 예측과정에서 정수배 화소 단위에서의 탐색에 비하여, 부화소 단위까지의 움직임 추정은 실제 움직임 벡터를 찾아낼 수 있지만, 이를 구하기 위한 계산량이 늘어나는 문제가 있다. 본 논문에서는 기준점을 기준으로 기준점으로부터 $\pm1$ 화소 내에서 두 번째로 작은 오차 값이 있는 특성 및 부화소 단위의 화소 보간 특성을 이용하여 움직임 추정 과정에서 탐색점을 줄임으로써 연산 처리 속도를 증가시키고, 계산의 복잡도를 줄이는 알고리즘을 제안하였다. 제안한 방법에서는 정수 화소 단위에서의 가장 작은 SATD를 갖는 점과 참조 영상으로부터 추출한 PMV를 비교하여 기준점을 정한 후, 기준점 주위의 8개의 화소 위치 가운데 두 번째로 SATD값이 작은 점을 찾아 해당 방향으로 1/2 화소 단위의 움직임 추정을 수행하였고, 1/4 화소 단위에서도 1/2 화소단위에서 두 번째로 SATD가 작은 점 방향으로 움직임 추정을 실행하였다. 그 결과 기존의 JM에서 사용한 고속 움직임 예측 알고리즘에 비해 PSNR값에 큰 변화가 없고, 움직임 벡터 예측 시간 면에서 약 18%의 시간을 줄이는 결과를 보였다.

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An Improved Motion Compensated Temporal Filtering for Efficient Scalable Video Coding (효율적인 스케일러블 비디오 부호화를 위한 향상된 움직임 보상 시간적 필터링 방법)

  • Jeon, Ki-Cheol;Kim, Jong-Ho;Jeong, Je-Chang
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.5C
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    • pp.520-529
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    • 2007
  • In this paper, we study the characteristics of parameters which are related to performance of MCTF which is a key technique for wavelet-based scalable video coding, and propose an improved MCTF method. The proposed MCTF method adopts the motion estimation of which motion vector field is distributed more uniformly using variable block sizes. By using the proposed method, the decomposition performance of temporal filter is improved, and the energy in high-frequency frames is reduced. It can help the entropy coder to generate lower bitrate. From simulation results, we verify the decomposed energy on high-frequency frame using the proposed method is reduced by 25.86% at the most in terms of variance of the high-frequency frame.

Video Shot Retrieval in H.264/AVC compression domain (H.264/AVC 압축 영역에서의 동영상 검색)

  • Byun Ju-Wan;Kim Sung-Min;Won Chee-Sun
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.43 no.5 s.311
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    • pp.72-78
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    • 2006
  • In this paper, we present a video shot retrieval algorithm in H.264/AVC compression domain. Unlike previous standards such as MPEG-2 and 4, H.264/AVC supports a variable block size for motion compensation. Therefore, existing video retrieval algorithms exploiting the motion vectors in MPEG-2 and 4 domains are not appropriate for H.264/AVC. So, we devise a method to project motion vectors with larger than $4{\times}4$ block sizes into those for the smallest $4{\times}4$ blocks. It also uses correlations among features for the measure of similarity. Experimental results with standard videos of 10558 frames and commercial videos of 48161 frames show that the proposed method yields ANMRR less than 0.2.

A Temporal Error Concealment Algorithm with Adaptive Block Size in the H.264/AVC Standard (H.264에서의 시방향(時方向) 에러은닉 기법)

  • Kim, Dong-Hyung;Jeong, Je-Chang
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.2C
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    • pp.49-58
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    • 2005
  • For the improvement of coding efficiency, the H.264 standard uses new coding tools. Using these coding tools, H.264 has achieved significant improvements from rate-distortion point of view. The adoption of these tools enables a macroblock in H.264 to have more information, sixteen motion vectors, four reference frames and a macroblock mode. In this paper, we present an efficient temporal error concealment algorithm by using not only motion vectors and reference frames but also macroblock mode of neighbor macroblocks. Our algorithm conceals the macroblock error with variable sizes, $16{\times}16,\;16{\times}8,\;8{\times}16,\;8{\times}8$ depending on the macroblock modes of neighbor macroblocks. Simulation results show that the proposed method increase the objective quality regardless of bit-rate and block error rate.

Fusion of Blockchain-IoT network to improve supply chain traceability using Ethermint Smart chain: A Review

  • George, Geethu Mary;Jayashree, LS
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.16 no.11
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    • pp.3694-3722
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    • 2022
  • In today's globalized world, there is no transparency in exchanging data and information between producers and consumers. However, these tasks experience many challenges, such as administrative barriers, confidential data leakage, and extensive time delays. To overcome these challenges, we propose a decentralized, secured, and verified smart chain framework using Ethereum Smart Contract which employs Inter Planetary File Systems (IPFS) and MongoDB as storage systems to automate the process and exchange information into blocks using the Tendermint algorithm. The proposed work promotes complete traceability of the product, ensures data integrity and transparency in addition to providing security to their personal information using the Lelantos mode of shipping. The Tendermint algorithm helps to speed up the process of validating and authenticating the transaction quickly. More so in this time of pandemic, it is easier to meet the needs of customers through the Ethermint Smart Chain, which increases customer satisfaction, thus boosting their confidence. Moreover, Smart contracts help to exploit more international transaction services and provide an instant block time finality of around 5 sec using Ethermint. The paper concludes with a description of product storage and distribution adopting the Ethermint technique. The proposed system was executed based on the Ethereum-Tendermint Smart chain. Experiments were conducted on variable block sizes and the number of transactions. The experimental results indicate that the proposed system seems to perform better than existing blockchain-based systems. Two configuration files were used, the first one was to describe the storage part, including its topology. The second one was a modified file to include the test rounds that Caliper should execute, including the running time and the workload content. Our findings indicate this is a promising technology for food supply chain storage and distribution.

A Fast Inter Prediction Encoding Technique for Real-time Compression of H.264/AVC (H.264/AVC의 실시간 압축을 위한 고속 인터 예측 부호화 기술)

  • Kim, Young-Hyun;Choi, Hyun-Jun;Seo, Young-Ho;Kim, Dong-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.11C
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    • pp.1077-1084
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    • 2006
  • This paper proposed a fast algorithm to reduce the amount of calculation for inter prediction which takes a great deal of the operational time in H.264/AVC. This algorithm decides a search range according to the direction of predicted motion vector, and then performs an adaptive spiral search for the candidates with JM(Joint Model) FME(Fast Motion Estimation) which employs the rate-distortion optimization(RDO) method. Simultaneously, it decides a threshold cost value for each of the variable block sizes and performs the motion estimation for the variable search ranges with the threshold. These activities reduce the great amount of the complexity in inter prediction encoding. Experimental results by applying the proposed method .to various video sequences showed that the process time was decreased up to 80% comparing to the previous prediction methods. The degradation of video quality was only from 0.05dB to 0.19dB and the compression ratio decreased as small as 0.58% in average. Therefore, we are sure that the proposed method is an efficient method for the fast inter prediction.

Design of High-Performance Motion Estimation Circuit for H.264/AVC Video CODEC (H.264/AVC 동영상 코덱용 고성능 움직임 추정 회로 설계)

  • Lee, Seon-Young;Cho, Kyeong-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.7
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    • pp.53-60
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    • 2009
  • Motion estimation for H.264/AVC video CODEC is very complex and requires a huge amount of computational efforts because it uses multiple reference frames and variable block sizes. We propose the architecture of high-performance integer-pixel motion estimation circuit based on fast algorithms for multiple reference frame selection, block matching, block mode decision and motion vector estimation. We also propose the architecture of high-performance interpolation circuit for sub-pixel motion estimation. We described the RTL circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The integer-pixel motion estimation circuit consists of 77,600 logic gates and four $32\times8\times32$-bit dual-port SRAM's. It has tile maximum operating frequency of 161MHz and can process up to 51 D1 (720$\times$480) color in go frames per second. The fractional motion estimation circuit consists of 22,478 logic gates. It has the maximum operating frequency of 200MHz and can process up to 69 1080HD (1,920$\times$1,088) color image frames per second.

Efficient Motion Estimation Algorithm and Circuit Architecture for H.264 Video CODEC (H.264 비디오 코덱을 위한 효율적인 움직임 추정 알고리즘과 회로 구조)

  • Lee, Seon-Young;Cho, Kyeong-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.12
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    • pp.48-54
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    • 2010
  • This paper presents a high-performance architecture of integer-pel motion estimation circuit for H.264 video CODEC. Full search algorithm guarantees the best results by examining all candidate blocks. However, the full search algorithm requires a huge amount of computation and data. Many fast search algorithms have been proposed to reduce the computational efforts. The disadvantage of these algorithms is that data access from or to memory is very irregular and data reuse is difficult. In this paper, we propose an efficient integer-pixel motion estimation algorithm and the circuit architecture to improve the processing speed and reduce the external memory bandwidth. The proposed circuit supports seven kinds of variable block sizes and generates 41 motion vectors. We described the proposed high-performance motion estimation circuit at R1L and verified its operation on FPGA board. The circuit synthesized by using l30nm CMOS standard cell library processes 139.8 1080HD ($1,920{\times}1,088$) image frames per second and supports up to H.264 level 5.1.

An Efficient Motion Estimation Method which Supports Variable Block Sizes and Multi-frames for H.264 Video Compression (H.264 동영상 압축에서의 가변 블록과 다중 프레임을 지원하는 효율적인 움직임 추정 방법)

  • Yoon, Mi-Sun;Chang, Seung-Ho;Moon, Dong-Sun;Shin, Hyun-Chul
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.5
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    • pp.58-65
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    • 2007
  • As multimedia portable devices become popular, the amount of computation for processing data including video compression has significantly increased. Various researches for low power consumption of the mobile devices and real time processing have been reported. Motion Estimation is responsible for 67% of H.264 encoder complexity. In this research, a new circuit is designed for motion estimation. The new circuit uses motion prediction based on approximate SAD, Alternative Row Scan (ARS), DAU, and FDVS algorithms. Our new method can reduce the amount of computation by 75% when compared to multi-frame motion estimation suggested in JM8.2. Furthermore, optimal number and size of reference frame blocks are determined to reduce computation without affecting the PSNR. The proposed Motion Estimation method has been verified by using the hardware and software Co-Simulation with iPROVE. It can process 30 CIF frames/sec at 50MHz.

Fast Intermode Decision for Scalable Video Coding using Statistical Hypothesis Testing (스케일러블 비디오 부호화에서 통계적 가설 검증 기법을 이용한 고속 화면간 모드 결정)

  • Lee, Bum-Shik;Hahm, Sang-Jin;Kim, Byung-Sun;Lee, Keun-Sik;Park, Keun-Soo;Kim, Mun-Churl
    • Journal of Broadcast Engineering
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    • v.12 no.3
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    • pp.250-265
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    • 2007
  • In this paper, a fast intermode decision scheme is introduced by efficiently performing the mode decision using statistical hypothesis testing for hierarchical B-picture coding of SVC, in which much computational power is expensed for combined variable block sizes and hierarchical B-pictures. The hypothesis testing in the proposed method is performed on $16{\times}16\;and\;8{\times}8$ blocks to have early termination for RD computation of all possible modes. The early termination in intermode decision is performed by comparing the pixel values of current blocks and corresponding motion-compensated blocks. The proposed scheme exhibits effective early termination behavior in intermode decision and leads to a significant reduction up to 69% in computational complexity with slight increment in bit amounts. The degradation of visual quality turns out to be negligible in terms of PSNR values.