• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.2
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• pp.7-15
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• 1983

In recent years, the logic circuits of high function have been developed to VLSI by the radical advancement of semi-conductor technologies. Under the above influence, it has become possible to design the special VLSI chips for high speed of numerical value processing, wide-band, image processing, etc. And, the development of the VLSI from various kinds of software package has become quite possible. This paper is to propose the technical skill of hardware design about general software package (BMD). The decrease of speed of former statistics processing caused by depending on software only is improved by hardware. In regard of design algorithm, the main system will be able to be established by considering of special feature of statistics. As a result, the complexity of software package is excluded by hardware. And, the efficiency is improved by high speed processing.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.119-123
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• 2001

In this paper, a new structure and fabrication method for the wafer level package(WLP) is presented. A packaged VLSI chip is encapsulated by a parylene(which is a low k material) layer as a dielectric layer and is molded by SUB photo-epoxy with dielectric constant of 3.0 at 100 MHz. The electrical parameters (R, L, C) of package traces are extracted by using the Maxwell 3-D simulator. Based on HSPICE simulation results, the proposed wafer level package can operate for frequencies up to 20GHz.

• Journal of Welding and Joining
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• v.16 no.5
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• pp.100-107
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• 1998

This paper describes fluxless soldering of reflow soldering process using solder foil instead of solder pastes. There is an increasing demand for the reliable solder connection in the recent high density microelectronic components technologies. And also, it is problem fracture of an Ozone layer due to freon as which is used to removal of remained flux on the substrate. This paper discussed joining phenomena, boudability and joining processes of microelectronics devices, such as between outer lead of VLSI package and copper pad on a substrate without flux. The shear strength of joints is 8 to 13 N using Sn/Pb (63/37 wt.%) solder foil with optimum joining conditions, meanwhile, in case of using Sn/In (52/48 wt.%) solder foil, it is possible to bond with low heating temperature of 550 K, and accomplish to high bonding strength of 25N in condition heating temperature of 650K. Finally, this paper experimentally shows fluxless soldering using solder foil, and accomplishes key technology of microsoldering processes.

• 전기의세계
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• v.38 no.7
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• pp.46-52
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• 1989

지금까지 Vector supercomputer를 비롯한 여러종류의 supercomputer의 기술발전 추세를 간단히 살펴보았다. 앞으로의 Supercomputer는 VLSI기술의 발달, GaAs같은 새로운 소재의 chip, optical connection을 이용한 더 나은 Package방식, 보다 큰 memory 그리고 parallel processing을 최대한 이용하여 현재의 supercomputer성능보다 엄청나게 강력한 Test FLOPS급의 성능을 발휘할 것으로 기대된다. 또한 전문분야별 Supercomputer들도 발전을 거듭하면서 성능은 크게 증가하고 값은 떨어져서 과학기술 분야를 포함한 각분야에 일상적으로 쓰이게 될 것이다.

• ETRI Journal
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• v.27 no.6
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• pp.691-696
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• 2005

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very-large-scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a $5{\times}5$ matrix of data cells in a Virtex-E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.29-37
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• 2006

This paper presents a new analytical model to suppress RLC resonance effects which inevitably occur in power/ground lines due to on-chip decoupling capacitor and other interconnect circuit parasitics (i.e., package inductance, on-chip decoupling capacitor, and output drivers, etc.). To characterize the resonance effects, the resonance frequency of the circuit is accurately estimated in an analytical manner. Thereby, a decoupling capacitor size to suppress the resonance for a suitable circuit operation is accurately determined by using the estimated resonance frequency. The developed novel design methodology is verified by using $0.18{\mu}m$ process-based-HSPICE simulation.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.435-438
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• 2004

This paper presents a new analytical model to suppress RLC resonance effects in power/ground lines due to a decoupling capacitor. First, the resonance frequency of an RLC circuit which is composed of package inductance. decoupling capacitor, and output drivers is accurately estimated. Next, using the estimated resonance frequency, a suitable decoupling capacitor sire is determined. Then, a novel design methodology to suppress the resonance effects is developed. Finally, its validity is shown by using $0.18 {\mu}m$ process-based-HSPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.92-98
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• 1996

parallel bonding wires separaated with a screeing bonding wire are proposed and characterized in order to redue mutual coupling and parasitics of high-speed and high-density device packaging. The mehtod of moments (MoM) with the incorporation of the ohmic loss has been used in a wide range of frequencies. From the calculated results, we have found that the screening bonding wire effectively reduces inductive and capacitive crostalk levels more than 3dB. the parasitic self inductance is also reduced more than 12% by the screening effect. Therefore, for a general VLSi package, the packaging density can be increased more than 30% using the screening bonding wire. This screeing bonding wire and the analysis can be effectively used to reduce crosstalk and increase packaging density of high density devices.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.37-39
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• 2001

21세기의 벽두부터 국내외적으로 활발히 논의되고 있는 나노기술에 대한 정의를 생각해보는 것으로부터 우리가 나아갈 방향을 살펴보고자 한다. 나노기술이란, 원자 하나 하나 혹은 분자단위의 조작을 통해 1~100nm정도의 범위 안에서 근본적으로 새로운 물질이나 구조체를 만들어 내는 기술을 말한다. 즉 앞으로 우리는 경험해 보지 못한 새로운 현상에 대한 이해를 할 수 있어야 하고, 새로운 물질 자체를 다룰 수 있는 방법이 우리가 해야 할 구체적인 일이 될 것이란 말이 된다. 뿐만 아니라 나노기술은 종래의 정보.통신.전자 분야에서 주로 추구하던 마이크로화와 달리 재료, 기계, 전자, 의학, 약학, 에너지, 환경, 화학, 생물학, 농학, 정보, 보안기술 등 과학기술 분야 전반을 위시하여 사회분야가지 새로운 인식과 철학적인 이해가 필요하게 되었다. 21세기를 맞은 인류가 나아갈 방향을 나노세계에 대한 도전으로 보아야 하며, 과학기술의 새로운 틀을 제공할 것 임에 틀림 없다. 그러나, 이와 같은 나노기술의 출발점을 살펴보면 VLSI기술로 통칭할 수 있는 마이크로전자소자 기술이란 점이다. 국내의 VLSI기술은 메모리기술이라고 해도 과언이 아닐 것이다. 문제는 종래의 메모리기술은 대규모 투자와 집중적인 인력양성을 통해서 세계 최고 수준에 도달 할 수 있었다. 그러나 여기까지 오는 동안 사식 우리는 선진국의 뒷꽁무니를 혼신의 힘을 다해 뒤쫓아 온 결과라고 보아도 틀리지 않는다. 즉, 앞선자를 보고 뒤쫓는 사람은 갈방향과 목표가 분명하므로 최선을 다하면 따라 잡을 수 있다. 그런데 나노기술은 앞선 사람이 없다는 점이 큰 차이이다 따라서 뒷껑무니를 쫓아가는 습성을 가지고는 개척해 나갈 수 없다는 점을 깨닫지 않으면 안된다. 그런 점에서 이 시간 나노기술의 국내외 현황을 살펴보고 우리가 어떻게 할 것인가를 생각해 보는데 의미가 있을 것이다.하여 분석한 결과 기존의 제한된 RICH-DP는 실시간 서비스에 대한 처리율이 낮아지며 서비스 시간이 보장되지 못했다. 따라서 실시간 서비스에 대한 새로운 제안된 기법을 제안하고 성능 평가한 결과 기존의 RICH-DP보다 성능이 향상됨을 확인 할 수 있었다.(actual world)에서 가상 관성 세계(possible inertia would)로 변화시켜서, 완수동사의 종결점(ending point)을 현실세계에서 가상의 미래 세계로 움직이는 역할을 한다. 결과적으로, IMP는 완수동사의 닫힌 완료 관점을 현실세계에서는 열린 미완료 관점으로 변환시키되, 가상 관성 세계에서는 그대로 닫힌 관점으로 유지 시키는 효과를 가진다. 한국어와 영어의 관점 변환 구문의 차이는 각 언어의 지속부사구의 어휘 목록의 전제(presupposition)의 차이로 설명된다. 본 논문은 영어의 지속부사구는 논항의 하위간격This paper will describe the application based on this approach developed by the authors in the FLEX EXPRIT IV n$^{\circ}$EP29158 in the Work-package "Knowledge Extraction & Data mining"where the information captured from digital newspapers is extracted and reused in tourist information context.terpolation performance of CNN was relatively better than NN.콩과 자연 콩이 성분 분석에서 차이를 나타내지 않았다는 점, 네 번째. 쥐를 통한 다양섭취 실험에서 아무런 이상 반응이 없었다는 점등의 결과를 기준으로 알레르기에 대한 개별 검사 없이 안전한