• 한국통신학회논문지
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• 제25권10A호
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• pp.1604-1612
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• 2000

본 논문에서는 VLSI설계를 위한 동시수행 하드웨어 할당 및 바인딩 알고리듬을 제안한다. 제안된 알고리듬은 스케쥴링 결과를 입력으로 받아들이고, 각 기능 연산자에 연결된 레지스터 및 연결 구조가 최대한 공유하도록 제어스텝마다 연산과 기억 소자의 상호연결 관계를 고려하여 기능 연산자, 연결 구조 및 레지스터를 동시에 할당 및 바인딩을 한다. 또한 레지스터 할당은 그래프 컬러링을 이용하여 최적의 레지스터 할당을 수행한다. 제안된 알고리듬은 실험 결과를 통해 기존의 기능 연산자와 레지스터의 수를 미리 정했거나, 분리하여 수행한 방식들과 비교함으로서 본 논문의 효율성을 보인다.

• 전자공학회논문지A
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• 제29A권1호
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• pp.48-59
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• 1992

This paper presents the design of a layout processing system that performs circuit and symbolic extraction from hierarchical designs containing arbitrarily shaped layout. The system is flexible enough to deal with various technologies, MOS or bipolar, by providing extraction rules in the form of technology files. In this paper, new efficient algorithms for trapezoidal decomposition of polygon and symbolic path extraction using trapezoidal template are proposed for symbolic extraction. Circuit and symbolic extractor is developed as an integrated design environment of SOLID system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.285-288
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• 2001

In this paper a design of cryptographic coprocessor which implements AES Rijndael algorithm is described. To achieve average throughput of 1 round per 5 clocks, subround pipelined scheme is applied. To apply the coprocessor to various applications, three key sizes such as 128, 192, 256 bits are supported. The cryptographic coprocessor is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology and consists of about 36, 000 gates. Its peak performance is about 512 Mbps encryption or decryption rate under 200 Mhz clock frequency and 128-bit key ECB mode(AES-128ECB).

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.938-941
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• 1999

In this paper, we designed a pipeline (15,9) Reed-solomon decoder. To compute the error locator polynomials, we used the Euclidean algorithm. This algorithm includes computation of inverse element. We avoided the inverse element calculation in this RS decoder by using ROMs. We designed this decoder using VHDL. Simulation results show that the designed decoder corrects three error symbols. We implemented this design through an Altera FPGA chip.

• 전력전자학회논문지
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• 제6권6호
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• pp.564-571
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• 2001

본 논문은 휴대용 기기를 위한 고효율의 저전압용 DC/DC 컨버터의 고집적회로에 관한 연구이다. 컨버터의 모든 능동 소자들은 0.65$\mu\textrm{m}$표준 CMOS 공정을 사용하여 단일 칩으로 구현하였다 수종 소자들의 크기를 줄이기 위해서 1MHz의 주파수에서 동작하며 높은 주파수에서 의스위칭 손실을 최소화하기 위하여 ZVS 방식으로 설계하였다. 시뮬레이션 결과 출력 전압이 2V일때 1W의 출력을 가지며 full 부하에서 95%의 효율을 보였다.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권6호
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• pp.316-321
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• 2000

In this paper, we proposed MBDD(Modified Binary Decision Diagram) as a multi-level logic synthesis method and a vertex of MBDD to NMOS transistors matching. A vertex in MBDD is matched to a set of NMOS transistors. MBDD structure can be achieved through transformation steps from BDD structure. MBDD can represent the same function with less vertices less number of NMOS transistors, consequently capacitance of the circuit can be reduced. Thus the power dissipation can be reduced. We applied MBDD to a full odder and a 4-2compressor. Comparing the 4-2compressor block with other synthesis logic, 31.2% reduction and 19.9% reduction was achieved in numbers of transistors and power dissipation respectively. In this simulation we used 0.8 ${\mu}{\textrm}{m}$ fabrication parameters.

• 전자공학회논문지B
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• 제32B권3호
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• pp.66-76
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• 1995

In this research, a mesh connected VLSI structure is proposed for the real time computation of the generalized Hough transform(GHT). The purpose of the research is to design a generalized Hough transformer that can be realized as a single chip processor. The GHT has been modified to yield a highly parallel structure consisting of simple processing elements(PEs) and communication networks. In the proposed structure, the GHT can be computed by first assigning an image pixel to a PE and performing shift and add operations. The result of the CAD circuit simulation shows that it can be computed in the time proportional to the number of pixels in the pattern. In addition to the Hough transformer, the peak detector has been designed to reduce 1)the number of the I/O operations between the transformer and the host computer and 2) the host computer's burden for peak detection by transmitting only the local peaks detected from the transformed accumulator. It is expected that the proposed single chip Hough transformer with peak detector makes a fast and inexpensive edge based object recognition systems possible for many industrial and military applications.

• 전자공학회논문지C
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• 제34C권8호
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• pp.22-38
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• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• 한국통신학회논문지
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• 제8권1호
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• pp.30-37
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• 1983

LSI CAD 시스템에 있어서 가장 중요한 휴러시틱 레이아웃 알고리즘을 제안하고 있다. 배치 알고리즘으로서는 인간이 작성한 논리설계회로 도면상의 모듈의 위치를 그대로 배치에 반영함으로써 인간의 종합판단력을 이용한 배치방법을 제안하였다. 제안된 방법의 유용성을 보이기 위해 종래 사용되고 있는 클러스터 성장배치법과 비교하는 프로그램 실험을 행하였다. 배선 알고리즘으로서는 종래 Maze법이 갖는 단점 즉 기억용량 과다문제를 줄이기 위한 방법을 제안했다.

• 전자공학회논문지A
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• 제30A권11호
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• pp.140-148
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• 1993

High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.