• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.10A
• /
• pp.1604-1612
• /
• 2000

This paper proposes a simultaneous hardware resource allocation and binding algorithm for VLSI design. The proposed algorithm works on scheduled input graph and simultaneously allocates binds functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. Also, the register allocation is especially executes the allocation optima us-ing graph coloring techniques. Therefore the overall resource is reduced. This paper shows the effectiveness of the proposed algorithm by comparing experiments to determine number of functional unit in advance or to separate executing allocation and binding of existing system.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.29A no.1
• /
• pp.48-59
• /
• 1992

This paper presents the design of a layout processing system that performs circuit and symbolic extraction from hierarchical designs containing arbitrarily shaped layout. The system is flexible enough to deal with various technologies, MOS or bipolar, by providing extraction rules in the form of technology files. In this paper, new efficient algorithms for trapezoidal decomposition of polygon and symbolic path extraction using trapezoidal template are proposed for symbolic extraction. Circuit and symbolic extractor is developed as an integrated design environment of SOLID system.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.285-288
• /
• 2001

In this paper a design of cryptographic coprocessor which implements AES Rijndael algorithm is described. To achieve average throughput of 1 round per 5 clocks, subround pipelined scheme is applied. To apply the coprocessor to various applications, three key sizes such as 128, 192, 256 bits are supported. The cryptographic coprocessor is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology and consists of about 36, 000 gates. Its peak performance is about 512 Mbps encryption or decryption rate under 200 Mhz clock frequency and 128-bit key ECB mode(AES-128ECB).

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.938-941
• /
• 1999

In this paper, we designed a pipeline (15,9) Reed-solomon decoder. To compute the error locator polynomials, we used the Euclidean algorithm. This algorithm includes computation of inverse element. We avoided the inverse element calculation in this RS decoder by using ROMs. We designed this decoder using VHDL. Simulation results show that the designed decoder corrects three error symbols. We implemented this design through an Altera FPGA chip.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.6 no.6
• /
• pp.564-571
• /
• 2001

This paper presents the VLSI design of highly efficient low voltage DC/DC converter for portable devices. All active devices are integrated on a single chip using a standard 0.65$\mu\textrm{m}$ CMOS process. The converter operates at the switching frequency of 1MHz for reducing the size of passive elements and uses a ZVS for minimizing the switching loss at high frequency. Simulation results show that the circuit can achieve a 95% efficiency when the output voltage is controlled to be 2V with the load of lW.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.49 no.6
• /
• pp.316-321
• /
• 2000

In this paper, we proposed MBDD(Modified Binary Decision Diagram) as a multi-level logic synthesis method and a vertex of MBDD to NMOS transistors matching. A vertex in MBDD is matched to a set of NMOS transistors. MBDD structure can be achieved through transformation steps from BDD structure. MBDD can represent the same function with less vertices less number of NMOS transistors, consequently capacitance of the circuit can be reduced. Thus the power dissipation can be reduced. We applied MBDD to a full odder and a 4-2compressor. Comparing the 4-2compressor block with other synthesis logic, 31.2% reduction and 19.9% reduction was achieved in numbers of transistors and power dissipation respectively. In this simulation we used 0.8 ${\mu}{\textrm}{m}$ fabrication parameters.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.32B no.3
• /
• pp.66-76
• /
• 1995

In this research, a mesh connected VLSI structure is proposed for the real time computation of the generalized Hough transform(GHT). The purpose of the research is to design a generalized Hough transformer that can be realized as a single chip processor. The GHT has been modified to yield a highly parallel structure consisting of simple processing elements(PEs) and communication networks. In the proposed structure, the GHT can be computed by first assigning an image pixel to a PE and performing shift and add operations. The result of the CAD circuit simulation shows that it can be computed in the time proportional to the number of pixels in the pattern. In addition to the Hough transformer, the peak detector has been designed to reduce 1)the number of the I/O operations between the transformer and the host computer and 2) the host computer's burden for peak detection by transmitting only the local peaks detected from the transformed accumulator. It is expected that the proposed single chip Hough transformer with peak detector makes a fast and inexpensive edge based object recognition systems possible for many industrial and military applications.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.8
• /
• pp.22-38
• /
• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.8 no.1
• /
• pp.30-37
• /
• 1983

In this paper I have proposed a heuristic layout algorism which is important in the CAD system of VLSI. I have designed a placement algorism to be used the method which depends upon the synthetic judgment of human. The placement algorism can reflect the position of a module in a logical design circuit diagram drawn up by human beings. Also, in order to show the usefulness of the new method I have compared through a program experiment it with the former method of cluster development placement. Moreover, a routing algorism is proposed in order to reduce the excessive problem of memory capacity. Of course this new algorism compensates for the former Maze's defects.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.30A no.11
• /
• pp.140-148
• /
• 1993

High Integration ratio of CMOS circuits incredily increases the test cost during the design and fabrication processes because of the FET fault(Stuck-on faults and Stuck-off faults) which are due to the operational characteristics of CMOS circuits. This paper proposes a test generation algorithm for an arbitrarily large CMOS circuit, which can unify the test steps during the design and fabrication procedure and be applied to both static and dynaic circuits. This algorithm uses the logic equations set for the subroutines resulted from arbitrarily dividing the full circuit hierarchically or horizontally. Also it involves a driving procedure from output stage to input stage, in which to drive a test set corresponding to a subcircuit, only the subcircuits connected to that to be driven are used as the driving resource. With this algorithm the test cost for the large circuit such as VLSI can be reduced very much.