• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.623-628
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• 1986

This paper reviews various CAD(Computer-Aided design) or DA(Design Automation) procedures for specification, design and verification of VLSI chips. The growth and widening of engineering achievements and applicational varieties in this revisited field has been truly explosive for the last five years. Recent trends in VLSI/CAD area and their possible implications on the future evolution of DA society are briefly touched upon. The relative importance of chip specification and design capability within the whole Korean electronics infrastructure in the future is explained with several possible suggestions for coping with upcoming difficulties already being seen in this challenging yet promising area.

• Proceedings of the Korean Society for Quality Management Conference
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• 1998.11a
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• pp.393-403
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• 1998

The advent of very large scale integration(VLSI) has had a tremendous impact on the design of fault-tolerant circuits and systems. The increasing density, decreasing power consumption, and decreasing costs of integrated circuits, due in part to VLSI, have made it possible and practical to implement the redundancy approaches used in fault-tolerant computing. The purpose of this paper is to study the many aspects of designing fault-tolerant systems in a VLSI environment. First, we expound upon the opportunities and problemes presented by VLSI technology. Second, we consider in detail the importance of design mistakes, common-mode failures, and transient faults in VLSI. Finally, we examine the techniques available to implement redundancy using VLSI and the problems associated with these techniques.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.22 no.53
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• pp.111-120
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• 1999

The advent of very large scale integration(VLSI) has had a tremendous impact on the design of fault-tolerant circuits and systems. The increasing density, decreasing power consumption, and decreasing costs of integrated circuits, due in part to VLSI, have made it possible and practical to implement the redundancy approaches used in fault-tolerant computing. The purpose of this paper is to study the many aspects of designing fault-tolerant systems in a VLSI environment. First, we expound upon the opportunities and problems presented by VLSI technology. Second, we consider in detail the importance of design mistakes, common-mode failures, and transient faults in VLSI. Finally, we examine the techniques available to implement redundancy using VLSI and the promlems associated with these techniques.

• Journal of the Korea Computer Industry Society
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• v.7 no.3
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• pp.205-215
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• 2006

In this paper, a method how to make Programmable Logic Array (PLA) design and inspection of circuit relative to recent 64bit microprocessor simple and easy was discussed. A design method using Random Access Memory (RAM), Read Only Memory (ROM) and PLA has been settled down in Very Large Scale Integrated Circuit (VLSI) and logical design, modifying circuit and inspection are easy in PLA so it holds fairly good advantages in the aspect of performance and cost. It is expected PLA will also occupy an important position as a basic factor in designing VLSI in the future.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.2
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• pp.7-15
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• 1983

In recent years, the logic circuits of high function have been developed to VLSI by the radical advancement of semi-conductor technologies. Under the above influence, it has become possible to design the special VLSI chips for high speed of numerical value processing, wide-band, image processing, etc. And, the development of the VLSI from various kinds of software package has become quite possible. This paper is to propose the technical skill of hardware design about general software package (BMD). The decrease of speed of former statistics processing caused by depending on software only is improved by hardware. In regard of design algorithm, the main system will be able to be established by considering of special feature of statistics. As a result, the complexity of software package is excluded by hardware. And, the efficiency is improved by high speed processing.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1098-1100
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• 2005

The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

• ETRI Journal
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• v.43 no.2
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• pp.260-271
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• 2021

This paper addresses Very large-scale integration (VLSI) placement optimization, which is important because of the rapid development of VLSI design technologies. The goal of this study is to develop a hybrid algorithm for VLSI placement. The proposed algorithm includes a sequential combination of a genetic algorithm and an evolutionary algorithm. It is commonly known that local search algorithms, such as random forest, hill climbing, and variable neighborhoods, can be effectively applied to NP-hard problem-solving. They provide improved solutions, which are obtained after a global search. The scientific novelty of this research is based on the development of systems, principles, and methods for creating a hybrid (combined) placement algorithm. The principal difference in the proposed algorithm is that it obtains a set of alternative solutions in parallel and then selects the best one. Nonstandard genetic operators, based on problem knowledge, are used in the proposed algorithm. An investigational study shows an objective-function improvement of 13%. The time complexity of the hybrid placement algorithm is O(N2).

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.419-420
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• 2000

This paper describes the innovation of VLSI design methodology in the coming decade. Technology trend of VLSI fabrication is surveyed first. Then the so-called “design crisis” is analyzed. Finally, possible design methodology to overcome the design crisis is discussed.

• The Transactions of the Korea Information Processing Society
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• v.2 no.3
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• pp.425-432
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• 1995

In this paper we propose a design and implementation technique of a universal automatic test pattern generator(UATPG) which is well suited for VLSI digital circuits. UATPG is designed to extend the capabilities of the existing APTG and to provide a convenient environment to computer-aided design(CAD) users. We employ heuristic techniques in line justification and fault propagation for functional gates during test pattern generation for a target fault. In addition, the flip-flops associated with design for testability (DFT) are exploited for pseudo PIs and pseudo POs to enhance the testabilities of VLSI circuits. As a result, UATPG shows a good enhancement in convenient usage and performance.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.100-100
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• 2004