• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.63-71
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• 2003

IDDQ testing is indispensable in improving Duality and reliability of CMOS VLSI circuits. But the major problem of IDDQ testing is slow testing speed due to time-consuming IDDQ current measurement. So one requirement is to reduce the number of target faults or to make the test sets compact in fault model. In this paper, we consider equivalent fault collapsing for transistor short faults, a fault model often used in IDDQ testing and propose an efficient algorithm for reducing the number of faults that need to be considered by equivalent fault collapsing. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.176-186
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• 1996

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

• Journal of the Korea Society of Computer and Information
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• v.6 no.1
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• pp.7-13
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• 2001

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently. IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. This paper presents a new BIC for the internal current test in CMOS logic circuit. Our circuit is composed of Magnetoresistive current sensor, level shifter, comparator, reference voltage circuit and a circuit be IDDQ tested as a kind of self-testing fashion by using the proposed BIC.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.23 no.60
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• pp.73-81
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• 2000

The testing processes for VLSI finished devices are considerably complex because they require different types of ATE to be linked together. Due to the interaction effect between two or more linked ATEs, it is difficult to trace down the cause of the unexpected longer ATE setup time and random yields, which frequently occur in the VLSI circuit-testing laboratory. The goal of this paper is to develop and demonstrate the methodology designed to eliminate the possible interaction factors that might affect the random yields and/or unexpected longer setup time as well as increase the productivity. The statistical method such as design of experiment or multivariate analysis cannot be applied to the final testing floor here directly due to the environmental constraints. Expanded product data information (PDI) is constructed by combining product data information and ATE control information. An architecture utilizing expanded PDI is designed, which enables the engineer to conduct statistical approach investigation and reduce the setup time, as well as increase yield.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1205-1214
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• 2004

For tile physical defects occurring in CMOS circuits which are not handled well by voltage-based testing, current testing is remarkable testing technique. Fault models based on defects must accurately describe the behaviour of the circuit containing the defect. In this paper, An efficient collapsing algorithm for fault models often used in current testing is proposed. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method in reducing the number of faults that have to be considered by fault collapsing and its usefulness in various current based testing models.

• Proceedings of the KSR Conference
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• 1998.05a
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• pp.408-418
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• 1998

This paper presents the implementation of comparator which is self-testing with respect to the faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it for the fault-tolerant system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on the designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper shows that these design, which has been implemented with 2 level AND-ORor NOR-NOR circuit, are optimal in term of size. And it also presents a formal proof that a comparator implemented using NOR-NOR PLA, based on these design, is sol f-testing with respect to most single faults in the presented fault model. Finally, it discusses the application of the self-testing comparator as a building block for the implementation of the fault-tolerant system.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2001.05a
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• pp.250-253
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• 2001

Mechanical properties of gold bonding wire for VLSI packaging have been studied. The diameters of gold wires are about 20-30 micrometer and fracture loads are 8-20 gram force. The elastic modulus, yield strength, fracture strength and elongation properties have been evaluated by micro-tensile test method. This work discusses for an appropriate selection of micro-force testing system and grip design in mim testing. The best method to determine gauge length of wire and to measure tensile properties has been proposed. The mechanical properties such as strength and elastic modulus of current gold bonding wire are higher than pure those of gold wire.

• Journal of the Korea Computer Industry Society
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• v.2 no.2
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• pp.219-228
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• 2001

This paper presents the implementation of comparator which are Fail-Safe with respect to faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it at the Fail-Safe system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper show that these design, which was implemented with 2 level AND_ORor NOR-NOR circuit, are optimal in term of size. And it also present a formal proof that a comparator implemented as NOR-NOR PLA, based on these design, is self-testing with respect to most single faults in the presented fault model. Finally, it discuss the application of the self-testing comparator as a building block for implementing Fail-Safe Adder.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.3_4
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• pp.160-169
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• 2004

With an emergence of SOC from developed IC technology, the VLSI design has required the core re-use technique and modular test development. To minimize the cost of testing SOC, an efficient method is required to optimize the test time and area overhead in conjunction for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient design strategy of core test wrapper to achieve the minimum cost for SOC testing. The proposed strategy adopted advantages of traditional methods and more developed to be successfully used in practice.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.11
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.