• Journal of the Korea Society of Computer and Information
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• v.3 no.4
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• pp.63-69
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• 1998

The area optimization of the power distribution network is an important problem in the layout design of VLSI systems. In this paper we propose noval methods to solve the problem of designing minimal area power distribution nets, while satisfying voltage drop and electromigration constraints. We propose two novel greedy heuristics for power net design-one based on bottom-up tree construction using greedy merging and the other based on top-down linearly separable partitioning.

• The Journal of the Korea Contents Association
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• v.21 no.7
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• pp.164-170
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• 2021

In VLSI design, partitioning is a task of clustering objects into groups so that a given objective circuit is optimized. It is used at the layout level to find strongly connected components that can be placed together in order to minimize the layout area and propagation delay. The most popular algorithms for partitioning include the Kernighan-Lin algorithm, Fiduccia-Mattheyses heuristic and simulated annealing. In this paper, we propose a adapted genetic algorithm searching solution space for the circuit partitioning problem, and then compare it with simulated annealing and genetic algorithm by analyzing the results of implementation. As a result, it was found that an adaptive genetic algorithm approaches the optimal solution more effectively than the simulated annealing and genetic algorithm.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.1
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• pp.73-77
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• 2007

In this paper, we propose a VLSI architecture of an LMS filter based on a Cyclo-static scheduler for fast computation of LMS filteing algorithm which is widely used in adptive filtering area. This process is composed of two steps: scheduling and circuit synthesis. The scheduling step accepts a fully specified flow graph(FSFG) as an input, and generates an optimal Cyclo-static schedule in the sense of the sampling rate, the number of processors, and the input-output delay. Then the generated schedule is transformed so that the number of communication edges between the processors. The circuit synthesis part translates the modified schedule into a complete circuit diagram by performing resource allocations. The VLSI layout generation can be performed easily by an existing silicon compiler.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.11
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• pp.66-73
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• 1993

This paper presents an analog circuit implementation and experimental resuls of the Hopfield type neural network. The proposed architecture enables the reconfiguration betwewn feedback and feedforward networks and employs new circuit designs for the weight supply and storage, analog multilier, nd current-voltage converter, in order to achieve area efficiency as well as function al versatility. The layout design of the eight-neuron neural network is tested as an associative memory to verify its applicability to real world.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.236-250
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• 2016

Electrical Designs for Application Specific Integrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1536-1539
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• 1987

This paper describes the method to extract CIF(Caltech Intermediate Form) by the digital image processing techniques from the VLSI chip. It is possible to represent to the layout editing system. The resolution of the image is 512 512 and 12 bits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.110-119
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• 1996

A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.8 no.1
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• pp.30-37
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• 1983

In this paper I have proposed a heuristic layout algorism which is important in the CAD system of VLSI. I have designed a placement algorism to be used the method which depends upon the synthetic judgment of human. The placement algorism can reflect the position of a module in a logical design circuit diagram drawn up by human beings. Also, in order to show the usefulness of the new method I have compared through a program experiment it with the former method of cluster development placement. Moreover, a routing algorism is proposed in order to reduce the excessive problem of memory capacity. Of course this new algorism compensates for the former Maze's defects.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.11a
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• pp.129-132
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• 2004

공간 색인구조는 공간 데이터를 효율적으로 관리하기 위한 도구로써, GIS와 같은 공간 데이터베이스의 성능을 결정하는 중요한 요소라 하겠다. 대부분의 응용분야에서 공간 데이터베이스는 보조기억장치에 저장된 방대한 양의 공간데이터 처리를 요구하므로 디스크 접근의 수를 줄이는 것이 전체 데이터베이스의 성능을 향상시키는데 중요한 요소이다. 이 논문에서는 SMR-tree라는 공간색인구조의 여러 응용분야에서 활용 가능성을 기존의 색인구조들과의 비교를 통해 확인한다. SMR-tree는 R-tree 계열의 구조로써 기존의 R-tree계열의 구조들과 동일한 노드의 형태를 가지고 있으나, 여러 개의 data space를 사용하여 data object를 배분함으로써 $R^{+}-tree$의 말단노드 내에 존재하는 잉여공간을 제거하면서 R-tree의 단점인 색인노드들 사이에 중첩을 허용치 않는다. SMR-tree의 성능은 여러 종류의 테스트 데이터(VLSI layout data, Tiger/Line file data)를 사용하여 R-tree, $R^{+}-tree,\;R^{\ast}-tree$와 비교된다. SMR-tree는 높은 공간 활용도와 다른 색인구조에 비해 빠른 질의 성능을 보임으로써 GIS와 같은 공간 데이터베이스를 위한 효율적인 색인구조로 사용이 될 것으로 기대된다.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11a
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• pp.433-436
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• 2002

VLSI 칩 설계는 매우 복잡한 공정이기 때문에 여러 단계, 즉 크게 분류하여 구조 설계, 논리 설계, 물리 설계 등의 과정을 거쳐 완성하게 된다. 그리고 각 단계에서는 그 단계에서 사용될 수 있는 소프트웨어의 도움을 받게 되며, 이런 소프트웨어의 도움 없이는 오늘날의 고밀도 칩 설계는 불가능하다. 각 단계에서 사용되는 소프트웨어의 주요한 기능 중 하나가 시뮬레이션 등을 통한 설계의 적합성을 테스트하는 것이라면 또 다른 주요한 기능은 설계자로 하여금 눈으로 확인하며, 변형된 설계의 일부를 눈으로 볼 수 있도록 보여주는 기능이라고 볼 수 있다. 논 본문에서는 칩 설계에서 가장 복잡한 단계라고 볼 수 있는 물리 설계 과정에 사용될 수 있는 Viewer를 설계하고 구현하여 제안한 Viewer를 통하여 회로의 정보를 보여 주며, 또한 상이한 레이아웃을 비교할 수 있도록 도와 준다. 설계된 Viewer 는 비록 초기버전이지만 물리 설계 단계에서 매우 중요한 정보, 예를 들어 critical net, 상이한 배치 등을 눈으로 확인하게 도와줌으로써 물리 설계에 관계된 다른 소프트웨어의 성능 개선을 유도할 수 있으며 또 실제 칩 설계 현장에서 바로 사용될 수 있기 때문에 실용성이 매우 높다.