• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.188-202
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• 1996

In this paper, we propose a symmetrical pseudo faulty processing elements genration technique to improve the overall reliability of arrays with fixed hardware resources on the fault tolerant VLSI arrays based on single-track switches. We have analyzed the reliability of fault tolerant VLSI arrays and designed control logic for real-tiem reconfiguration. Applying this technique to reconfiguration of VLSI 2-D arrays, we have found that the proposed scheme achieves a higher reliability than the previus methods of similar condition. And we have found that the results of reliability analyzed by mathematic computation are very close to simulated ones. Furthermore, the time overhead for reconfiguration is independent of the array size because the control for reconfiguration is distributively executed by each processing elements. And the proposed scheme has an advantage which maintained properties of VLSI arrays by keeping the locality of interconnections as high as possible even after the reconfiguration.

• Journal of the Korea Computer Industry Society
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• v.7 no.3
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• pp.205-215
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• 2006

In this paper, a method how to make Programmable Logic Array (PLA) design and inspection of circuit relative to recent 64bit microprocessor simple and easy was discussed. A design method using Random Access Memory (RAM), Read Only Memory (ROM) and PLA has been settled down in Very Large Scale Integrated Circuit (VLSI) and logical design, modifying circuit and inspection are easy in PLA so it holds fairly good advantages in the aspect of performance and cost. It is expected PLA will also occupy an important position as a basic factor in designing VLSI in the future.

• Information and Communications Magazine
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• v.9 no.11
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• pp.47-52
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• 1992

신경망 실용화에 기본이 되는 신경망 VLSI 기술의 최근 발전 추세에 관하여 검토하였다. 대규모 고속 신경망 VLSI 구현 방법들인 디지털, 아날로그, 하이브리드 신경망 칩들을 비교하였으며, 십 수만 단위의 하이브리드 신경망 칩기술을 제시하였다.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.78-85
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• 1998

In this paper we propose a VLSI implementation technique for camcorder's digital zooming system. The proposed VLSI includes the system clock(CLK), vertical drive(VD), horizontal drive(HD),blank(BLK), and field(FLD) signals as inputs, and produces magnified image as an output, with 256 different magnification ratios. In general, the above mentioned input signals are provided by the CCD driving IC in most camcorders. As a result, the proposed digital zooming VLSI can magnify a part of the input image by up to 256 times, where the magnification ratio can be chosen among 256 different steps. In the application point of view, the proposed VLSI can be used in any digital camcorder for realizing near continuous step digital zooming without any additional circuitry, such as micom or a general purpose digital signal processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.364-370
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• 2002

In this paper, we propose a VLSI array architecture for high speed processing of FBMA. First of all, the sequential FBMA is transformed into a single assignment code by using the index space expansion, and then the dependance graph is obtained from it. The two dimensional VLSI array is derived by projecting the dependance graph along the optimal direction. Since the candidate blocks in the search range are overlapped with columns as well as rows, the processing elements of the VLSI array are designed to reuse the overlapped data. As the results, the number of data inputs is reduced so that the processing performance is improved. The proposed VLSI array has (N$^2$+1)${\times}$(2p+1) processing elements and (N+2p) input ports where N is the block size and p is the maximum search range. The computation time of the rat reference block is (N$^2$+2(p+1)N+6p), and the block pipeline period is (3N+4p-1).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.265-268
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• 2001

In this paper, we designed one-dimensional VLSI array with high speed processing in Fractal image compression. fractal image compression algorithm partitions the original image into domain blocks and range blocks then compresses data using the self similarity of blocks. The image is partitioned into domain block with 50% overlapping. Domain block is reduced by averaging the original image to size of range block. VLSI array is trying to search the best matching between a range block and a large amount of domain blocks. Adjacent domain blocks are overlapped, so we can improve of each block's processing speed using the reuse of the overlapped data. In our experiment, proposed VLSI array has about 25% speed up by adding the least register, MUX, and DEMUX to the PE.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.156-163
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• 1996

In this paper, we propose VLSI architectures for the full search block matching algorithm (FS BMA) and two-stage BMA using integral projections that reduce greatly computational complexity with its performance comparable to that of the FS BMA. The proposed VLSI architectures are faster than the conventional ones with lower hardware complexity. Also the proposed architectures of the FS BMA and two-stage BMA are modeled in VHDL and simulated to show their functional validity.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.623-628
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• 1986

This paper reviews various CAD(Computer-Aided design) or DA(Design Automation) procedures for specification, design and verification of VLSI chips. The growth and widening of engineering achievements and applicational varieties in this revisited field has been truly explosive for the last five years. Recent trends in VLSI/CAD area and their possible implications on the future evolution of DA society are briefly touched upon. The relative importance of chip specification and design capability within the whole Korean electronics infrastructure in the future is explained with several possible suggestions for coping with upcoming difficulties already being seen in this challenging yet promising area.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10a
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• pp.667-669
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• 1999

최근 VLSI 디자인의 비용과 복잡성은 디자인 과정에서 필수조건이다. 소자 모델링과 수치적 방법은 spice와 같은 회로 시뮬레이터를 사용하여 얻을 수 있으며 simulated annealing과 같은 기법의 기술적인 장점은 많은 부분에서 응용된다. 이러한 기법들은 다량의 메모리 제조와 소규모 연구의 프로젝트까지 거의 모든 칩 디자인에 사용된다. 따라서 본 논문에서는 VLSI 회로의 패턴 매칭에 관한 역트랙킹(backtracking) 깊이-우선 탐색을 할 수 있는 그래프 탐색 매칭 알고리즘을 제안하였다.

• Journal of Korean Electronics
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• v.5 no.5
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• pp.66-75
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• 1985