• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1099-1101
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• 2000

ASIC chip design for motor control has been a subject of increasing interest since an effective methodology of system-on-a-chip design was developed. This paper investigates the design and implementation of ASIC chip for vector control of induction motor using VHDL which is a standard hardware description language. The vector control algorithm is finally implemented using a simple electronic circuit based on FPGA. The performance of the designed ASIC is verified through simulation and experiment.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1102-1104
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• 2000

Recently effective system-on-a-chip design methodology is developed, and ASIC chip design is much studied for motor control. This paper investigates the design and implementation of ASIC chip for sensorless speed control of induction motor using VHDL which is a standarded hardware description language. The sensorless control strategy is to design an adaptive state observer for flux estimation and to estimate the rotor speed from the estimated rotor flux and stator current. The presented system is implemented using a simple electronic circuit based on FPGA.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.169-172
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• 2001

In this paper, it used a different pipeline method from conventional method which is encoding the video signal of analog with digital. It designed with pipeline structure of 4 phases as the pixel clock ratio of the whole operation of the encoder, and secured the stable operational timing of the each sub-blocks, it was visible the effect which reduces a gate possibility as designing by the ROM table or the shift and adder method which is not used a multiplication flag method of case existing of multiplication of the fixed coefficient. The designed encoder shared with the each sub-block and it designed the FPGA using MAX+PLUS2 with VHDL.

• Annual Conference of KIPS
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• 2004.11a
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• pp.187-190
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• 2004

This paper proposes an efficient hardware implementation of SPIHT(Set Partitoning In Hierarchical Tree) algorithm for image compression with the discrete wavelet transform. An efficient technique to scan the coefficients which are located in partitioned spatial orientation trees by DWT is considered in terms of counter fields for sorting pass and refinement pass. The proposed image compression method using SPIHT has been modeled in VHDL and has been implemented by use of both TMS320C6000 as a DSP and Virtex2 as a Xilinx FPGA.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.280-283
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• 2003

어레이 셀 내의 연산에 대한 고성능 처리는 시스톨릭 어레이의 중요한 특징이다. 본 논문에서는 시스톨릭 어레이 구조 내 셀이 또 다른 시스톨릭 어레이 구조를 가지는 슈퍼 시스톨릭 어레이 구조를 제안하고, 그 예로 비트 레블 슈퍼 시스톨릭 정렬기의 설계 및 구현에 대하여 기술한다. 먼저 정규순환방정식으로 표현된 정렬 알고리즘으로부터 워드 레블 1차원 평면 시스톨릭 어레이를 유도한 후 유도된 워드 레블 시스톨릭 어레이를 슈퍼 시스톨릭 어레이로 변환한다. 위의 과정으로 유도된 비트 레블 슈퍼 시스톨릭 정렬기를 RT수준에서 VHDL로 모델링 하여 동작을 검증하였으며, 검증된 비트 레블 슈퍼 시스톨릭 정렬기는 Hynix에서 제공되는 0.35$\mu\textrm{m}$ 셀 라이브러리와 FPGA V200E칩을 사용하여 합성 및 구현되었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.890-893
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• 2006

동영상과 관련된 멀티미디어가 많은 관심을 받으며 영상 압축 기술에 대한 관심이 높아지고 있는 가운데, 최근 다른 표준보다 두 배 이상 좋은 새로운 비디오 코딩 표준인 H.264/AVC의 압축 기술이 발표되었다. 이 기술은 지상파 DMB와 PMP, 카메라폰 그리고 핸드폰의 게임과 음악 및 영상에 관련된 컨텐츠에서 고품질의 영상을 보다 효율적으로 제공한다. 이에 본 논문에서는 H.264/AVC의 부호화 과정에서 발생하는 오류로 인한 블록화를 최소화하기 위해 사용되는 deblocking 필터의 메모리와 처리속도의 향상을 제안하였다. 27*32SRAM을 사용하여 Vertical edge를 모두 처리하고 Horizontal edge를 처리하는 방식이 아닌 한 블록에 대한 Vertical edge후에 바로 Horizontal edge를 처리함으로써 28(prebuffering)19(Y)+32(Cb)+32(Cr)=188clocks에 $16\times16$ 블록 처리가 완료되는 deblocking 필터를 제안하여 하드웨어 설계언어인 VHDL언어로 설계하였다. 그리고 FPGA칩인 XCV1000E에 다운로드하여 칩 레벨의 시뮬레이션을 수행함으로써 설계된 deblocking 필터를 검증하였다.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.8 no.4
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• pp.21-32
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• 1998

통신 및 컴퓨터 시스템의 처리 속도가 높아짐에 따라 정보 보호를 위해서 고속의 데이터처리가 반드시 요구되어진다. 따라서 본 논문에서는 국제 표준 암호알로기즘의 하나인ISDEA(International Data Encryption Algorithm)를 고속 연산을 위하여 알고리즘을 분석하고 암호화 수행시간을 감소하기 위하여 파이프라인 처리를 하며, 서브키 생성시의 연산회수를 줄이기 위하여 서브키 블록을 EEPROM 으로 구현하였다. 전체적인 시스템은 VHDL(VHSIC Hardware Description Language)을 사용하여 설계하였다. IDEA 알고리듬은 EDA tool인 Synopsys를 사용하여 Sunthesis하였으며, Xilinx의 FPGA XC4052XL을 이용하여 One CHip화 시켰다. 입력 클럭으로 20Mhz를 사용하였을 때, data arrival time은 687.07ns였으며, 109.01 Mbp의 속도로 동작하 였다.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1022-1027
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• 2003

The Motion controllers provide the sophisticated performance and enhanced capabilities we can see in the movements of robotic systems. Several types of motion controllers are available, some based on the kind of overall control system in use. PLC (Programmable Logic Controller)-based motion controllers still predominate. The many peoples use MCU (Micro Controller Unit)-based board level motion controllers and will continue to in the near-term future. These motion controllers control a variety motor system like robotic systems. Generally, They consist of large and complex circuits. PLC-based motion controller consists of high performance PLC, development tool, and application specific software. It can be cause to generate several problems that are large size and space, much cabling, and additional high coasts. MCU-based motion controller consists of memories like ROM and RAM, I/O interface ports, and decoder in order to operate MCU. Additionally, it needs DPRAM to communicate with host PC, counter to get position information of motor by using encoder signal, additional circuits to control servo, and application specific software to generate a various velocity profiles. It can be causes to generate several problems that are overall system complexity, large size and space, much cabling, large power consumption and additional high costs. Also, it needs much times to calculate velocity profile because of generating by software method and don't generate various velocity profiles like arbitrary velocity profile. Therefore, It is hard to generate expected various velocity profiles. And further, to embed real-time OS (Operating System) is considered for more reliable motion control. In this paper, the structure of chip-based precision motion controller is proposed to solve above-mentioned problems of control systems. This proposed motion controller is designed with a FPGA (Field Programmable Gate Arrays) by using the VHDL (Very high speed integrated circuit Hardware Description Language) and Handel-C that is program language for deign hardware. This motion controller consists of Velocity Profile Generator (VPG) part to generate expected various velocity profiles, PCI Interface part to communicate with host PC, Feedback Counter part to get position information by using encoder signal, Clock Generator to generate expected various clock signal, Controller part to control position of motor with generated velocity profile and position information, and Data Converter part to convert and transmit compatible data to D/A converter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.62-71
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• 2001

This paper presents a design of the real-time digital image enhancement preprocessor for CMOS image sensor. CMOS image sensor offers various advantages while it provides lower-quality images than CCD does. In order to compensate for the physical limitation of CMOS sensor, the spatially adaptive contrast enhancement algorithm was incorporated into the preprocessor with color interpolation, gamma correction, and automatic exposure control. The efficient hardware architecture for the preprocessor is proposed and was simulated in VHDL. It is composed of about 19K logic gates, which is suitable for low-cost one-chip PC camera. The test system was implemented on Altera Flex EPF10KGC503-3 FPGA chip in real-time mode, and performed successfully.