• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.09b
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• pp.122-125
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• 2003

By advent of NNC(Neural Network Chip), it is possible that process in parallel and discern the importance of signal with learning oneself by experience in external signal. So, the design of general purpose operation unit using VHDL(VHSIC Hardware Description Language) on the existing FPGA(Field Programmable Gate Array) can replaced EN(Expert Network) and learning algorithm. Also, neural network operation unit is possible various operation using learning of NN(Neural Network). This paper present general purpose operation unit using hierarchical structure of EN EN of presented structure learn from logical gate which constitute a operation unit, it relocated several layer The overall structure is hierarchical using a module, it has generality more than FPGA operation unit.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.411-414
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• 2010

본 논문은 비디오 처리를 위한 고성능의 메모리 제어기를 설계하였다. 메모리 제어기는 arbiter에 의해 제어되며 이것은 메모리 억세스를 요구하는 모듈들의 요구 신호를 받아 데이터를 전송하는 역할을 해주게 된다. 구현된 메모리 제어기는 버스를 사용하기 위한 승인을 받기 위해서 마스터와 신호를 주고 받는 MAU블록, grant 신호를 디코딩하고 컨트롤 신호의 상태를 정의한 arbiter 블록, SDRAM의 ac parameter를 저장하고 bank의 준비 여부, read/write 가능 여부, precharge와 refresh의 가능 여부를 확인하여 system과 read/write가 준비되었다는 신호를 출력, SDRAM의 실질적인 입력신호를 생성하는 memory accelerator 블록, 생성된 입력신호를 저장하고 마스터에서 직접 write data를 입력 받는 memory I/F 블록으로 구성된다. 이 메모리 제어기는 174.28MHz의 주파수로 동작하였다. 본 설계는 VHDL을 이용하여 설계되었고, ALTERA의 Quartus II를 이용하여 합성하였다. 또한 ModelSim을 이용하여 설계된 회로를 검증하였다. 구현된 하드웨어는 StatixIII EP3SE80F1152C2 칩을 사용하였다.

• Review of KIISC
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• v.16 no.3
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• pp.25-33
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• 2006

본 논문에서는 임베디드 시스템 온칩 적용을 위한 통합 보안 프로세서를 SIP(Semiconductor Intellectual Property)로 설계하였다. 각각의 SIP는 VHDL RTL로 모델링하였으며, 논리합성, 시뮬레이션, FPGA 검증을 통해 재사용이 가능하도록 구현하였다. 또한 ARM9과 SIP들이 서로 통신이 가능하도록 AMBA AHB의 스펙에 따라 버스동작모델을 설계, 검증하였다. 플랫폼기반의 통합 보안 SIP는 ECC, AES, MD-5가 내부 코어를 이루고 있으며 각각의 SIP들은 ARM9과 100만 게이트 FPGA가 내장된 디바이스를 사용하여 검증하였으며 최종적으로 매그나칩 $0.25{\mu}m(4.7mm\times4.7mm)$ CMOS 공정을 사용하여 MPW(Multi-Project Wafer) 칩으로 제작하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1219-1225
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• 2001

In this Paper we describe the design of synchronization algorithms for burst QPSK receiver, which are applicable to BWLL uplink. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we ufo Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.212-214
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• 2005

The MDDI(Mobile Digital Display Interface) standard is an optimized high-speed serial interconnection technology developed by Qualcomm and supports the VESA(Video Electronics Standard Association). It increases reliability and reduces power consumption in clamshell phones by decreasing the number of wires to interconnect with the LCD display. In this paper, the MDDI host is designed using VHDL and implemented on FPGA. We demonstrates that the MDDI host is connected with S3CA460 LCD controller is designed by Samsung Electronics Co. and display a steal image to the LCD.

• Journal of Power Electronics
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• v.6 no.2
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• pp.114-120
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• 2006

This paper compares two types of direct torque controllers for permanent magnet synchronous motors(PMSMs). These controllers both use a single-chip FPGA(Field Programmable Gate Array) but have differing hardware configurations. One of the controllers was constructed by programming a soft-core CPU and hardware logic circuits written in VHDL(Very high speed IC Hardware Description Language), while the other was constructed of only hardware logic circuits. The characteristics of these two controllers were compared in this paper. The results show the controller constructed of only hardware logic circuits was able to shorten the control period and it was able to suppress the low torque ripple.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.666-669
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• 2002

A microprocessor with genetic instructions such as crossover, mutation and inversion is proposed. The processor is modeled using VHDL, synthesized to a schematic and implemented on a FPGA. The control path is implemented with a microprogram consisting of about 15032-bit microwords, and the operation of each instruction is checked through simulation.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.262-265
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• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk provides double error detecting and correcting capability. The most complex circuit in the RS decoder is part for solving the error location numbers from error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and Performed logic synthesis using the SYNOPSYS CAD tool. Then, the RS decoder has been implemented with FPGA. The total umber of gate is about 11,000 gates and it operates at 20MHz.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.95-98
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• 2004

In this paper, the hardware design of a transmission convergence sublayer(TC) for boradband wireless access system is described, which performs (1) formatting TC PDUs to MAC PDUs, (2) RS encoding/decoding, (3) providing various control signal to PHY modem. The TC hardware has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1997.11a
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• pp.205-213
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• 1997

본 논문에서는 암호화 알고리즘의 표준으로 자리잡은 DES(Data Encryption Standard) 알고리즘을 시스템 설계 기술언어인 VHDL을 이용하여 top-down 방식으로 설계하고 시뮬레이션을 수행하여 암ㆍ복호화의 결과를 보여준다. 또한 이것을 FPGA로 구현함으로써 하드웨어가 차지하는 면적과 속도를 산출 비교하여 암호화 속도 및 크기의 최적화를 위한 설계 방식을 제안한다. 본 논문에서는 최종적으로 V-system을 이용하여 시뮬레이션을 수행하고 Synopsys의 EDA 툴을 이용하여 합성을 한 후에 Xilinx사의 xdm을 이용하여 XC4025E에 칩으로 구현하였다.