• Journal of the Korea Institute of Information Security & Cryptology
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• v.8 no.3
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• pp.79-94
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• 1998

본 논문에서는 컴퓨터 시스템에서 정보보호를 위해 가장 많이 사용하고 있는 DES(Data Encryption Standard)암호알고리즘을 시스템 설계 기술언어인 VHDL(Vhsic Hardware Description Language)로 설계하고 이것을 칩으로 합성하여 하드웨어에서 차지하는 면적과 속도를 비교 분석하였다. 설계방법에 있어서는 구현하는 방법에 따라 전 라운드 구현형, S-box 공유형 그리고 단일 라운드 반복형 범용성을 갖도록 하여 FPGA로 구현한다. 본 논문에서 구현한 단일 라운드 반복형 설계는 Synopsys의 EDA 툴을 이용하여 시뮬레이션 및 합성을 하였고, Xilinx사의 xdm을 이용하여 XC4052XL 칩에 구현하였다. 그 결과 입력 클록 50MHz상에서 100Mbps의 암,복호화 속도를 갖는 범용성 암호칩을 설계 및 구현한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.869-872
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• 2008

This paper presents the VHDL implementation procedure of the passive RFID tag in Ultra High Frequency RFID system. The operation of the tag compatible with the EPCglobal Class1 Generation2(GEN2) protocol is verified by timing simulation after synthesis and implementation on prototyping board. Due to the reading range with relatively large distance, a passive tag needs digital processor which facilitates faster decoding, encoding and state transition for enhancement of the interrogation rate. Also with UART communication, verify a inventory Round in Gen2 Protocol. The verification results with the fastest data rate, 640kbps, and multi tags environment scenario show that the implemented tag spend 1.4ms transmitting the 96bits EPC to reader.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• The Journal of the Acoustical Society of Korea
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• v.37 no.4
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• pp.215-222
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• 2018

This paper reports the development and performance evaluation of a backend system for real-time IVUS (Intravascular Ultrasound) imaging. The developed backend system was designed to minimize the amount of logic and memory usage by means of efficient LUTs (Look-up Tables), and it was implemented in a single FPGA (Field Programmable Gate Array) without using external memory. This makes it possible to implement the backend system that is less expensive, smaller, and lighter. The accuracy of the backend system implemented was evaluated by comparing the output of the FPGA with the result computed using a MATLAB program implemented in the same way as the VHDL (VHSIC Hardware Description Language) code. Based on the result of ex-vivo experiment using rabbit artery, the developed backend system was found to be suitable for real-time intravascular ultrasound imaging.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.175-182
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• 2011

In this paper, we implemented a high-performence memory controller which can accommodate processing blocks(multiple masters) in SoC for video signal processing. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Selector, Mster Arbiter, Memory Signal Generator, Command Decoder, and memory Signal Generator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used. Since the designed H/W can be stably operated in 174.28MHz, it satisfies the specification of SDRAM technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3C
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• pp.215-223
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• 2003

Turbo codes are selected as FEC(Forward error correction) codes with convolution code in 3GFP(3rd generation partnership project) and 3GPP2 standard of IMT2000. Especially, l/3 turbo code with K=4 is employed for 3GPP standard. In this paper, we proposed a hardware structure of a turbo decoder and denveloped the decoder for 3GPP standard turbo code. For its efficient operation, we design a SOVA decoder by employing a register exchange decoding block and new path metric normalization block as a SISO constituent decoder. In addition, we estimate its performance under MATLAB 6.0 and designed the turbo decoder including control block, input control buffer, SOVA constituent decoder with VHDL. Finally, we synthesized the developed turbo decoder under Synopsys FPGA Express and verified it with ALTERA EPF200SRC240-3 FPGA device.

• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.1-6
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1016-1021
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• 2003

The overall size of electronic product is becoming small according to development of technology. Accordingly it is difficult to inspect these small components by human eyes. So, an automation system for inspecting them has been used. The existing system put microprocessor or Programmable Logic Controller (PLC) use. The structure of microprocessor-based controller and PLC use basically composed of memory devices such as ROM, RAM and I/O ports. Accordingly, the system is not only becomes complicated and enlarged but also higher price. In this paper, we implement FPGA-based One-chip Programmable Timing Controller for Inspecting Small components to resolve above problems and design the high performance controller by using VHDL. With fast development, the FPGA of high capacity that can have memory and PLL have been introduced. By using the high-capacity FPGA, the peripherals of the existent controller, such as memory, I/O ports can be implemented in one FPGA. By doing this, because the complicated system can be simplified, the noise and power dissipation problems can be minimized and it can have the advantage in price. Since the proposed controller is organized to have internal register, counter, and software routines for generating timing signals, users do not have to problem the details about timing signals and need to only send some values about an inspection system through an RS232C port. By selecting theses values appropriate for a given inspection system, desired timing signals can be generated.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.80-83
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• 2001

이족로봇이 stand-alone 형태를 가지기 위해서는 기계적인 구조가 중요할 뿐만 아니라 하드웨어시스템이 간결하게 잘 설계되어야 한다. 이렇게 하드웨어시스템이 가볍고 간결하여 설계되어야 쉽게 로봇에 장착할 수가 있다. 본 논문에서는 FPGA(Field Programmable Gate Array)를 이용해 모터 제어기를 구성해서 이족로봇을 설계하는 방법을 다루고자 한다. 본 논문에서 구성하는 하드웨어 시스템은 메인 CPU로 AM186ES를 사용하며 FPGA는 Altera사의 FLEX EPF10K20TC144-3을 사용하였다. 이와 같이 FPGA를 사용하는 하드웨어시스템은 기본적으로 VHDL언어를 사용하여 유연하게 하드웨어를 구성 할 수 있으며, 이족로봇의 여러 가지 보행 알고리즘에 능동적으로 대처할 수 있다. 뿐만 아니라 하드웨어가 간단해 지면서 가볍고 전력소모가 적으며 신뢰성 있는 시스템을 구축할 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.109-116
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• 2003

In this paper. we Propose an UXGA class LCD controller for controlling the LCD panel. The proposed controller supports the full screen display using GCD between input and output resolutions. The proposed LCD controller includes the motion detector based on median filter which can detect the motion of input image for the enhancement of a image quality. Also, it divides the motion into 3 stages such as still, semi-moving and moving, and uses the different interpolation algorithms according to the degree of motion. In order to evaluate the performance of the proposed interpolation algorithm, we use PSNR method and compare the conventional algorithm by using computer simulation. For the proposed motion detection algorithm, we use a visual verification and the estimation of pixel changes. The proposed LCD controller has been designed and verified by VHDL. It has been synthesized using Xilinx VirtexE FPGA.