• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.341.1-341.1
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• 2014

In the advanced material for the next generation display device, transparent amorphous oxide semiconductors (TAOS) are promising materials as a channel layer in thin film transistor (TFT). The TAOS have many advantages for large-area application compared with hydrogenated amorphous silicon TFT (a-Si:H) and organic semiconductor TFT. For the reasonable characteristics of TAOS, The a-IGZO has the excellent performances such as low temperature fabrication (R.T~), high mobility, visible region transparent, and reasonable on-off ratio. In this study, we investigated how the electric characteristics and physical properties are changed as various oxygen ratio when magnetron sputtering. we analysis a-IGZO film by AFM, EDS and I-V measurement. decreasing the oxygen ratio, the threshold voltage is shifted negatively and mobility is increasing. Through this correlation, we confirm the effect of oxygen ratio. We fabricated the bottom-gate a-IGZO TFTs. The gate insulator, SiO2 film was grown on heavily doped silicon wafer by thermal oxidation method. a-IGZO channel layer was deposited by RF magnetron sputtering. and the annealing condition is $350^{\circ}C$. Electrode were patterned Al deposition through a shadow mask(160/1000 um).

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2013.04a
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• pp.454-459
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• 2013

For the purpose of rapid development and superior design quality assurance, sophisticated finite element model for SOM(Spatial Optical Modulator) piezo actuator of MOEMS device has been developed and evaluated for the accuracy of dynamics and residual stress analysis. Parametric finite element model is constructed using ANSYS APDL language to increase the design and analysis performance. Geometric dimensions, mechanical material properties for each thin film layer are input parameters of FE model and residual stresses in all thin film layers are simulated by thermal expansion method with psedu process temperature. $6^{th}$ mask design samples are manufactured and $1^{st}$ natural frequency and 10V PZT driving displacement are measured with LDV. The results of experiment are compared with those of the simulation and validate the good agreement in $1^{st}$ natural frequency within 5% error. But large error over 30% occurred in 10V PZT driving displacement because of insufficient PZT constant $d_{31}$ measurement technology.

• Electrical & Electronic Materials
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• v.10 no.10
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• pp.1029-1033
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• 1997

A prototype MFSFET using ferroelectric fluoride BaMgF$_4$as a gate insulator has been successfully fabricated with the help of 2 sheets of metal mask. The fluoride film was deposited in an ultrai-high vacuum system at a substrate temperature of below 30$0^{\circ}C$ and an in-situ post-deposition annealing was conducted for 20 seconds at $650^{\circ}C$ in the same chamber. The interface state density of the BaMgF$_4$/Si(100) interface calculated by a MFS capacitor fabricated on the same wafer was about 8$\times$10$^{10}$ /cm$^2$.eV. The I$_{D}$-V$_{G}$ characteristics of the MFSFET show a hysteresis loop due to the ferroelectric nature of the BaMgF$_4$film. It is also demonstrated that the I$_{D}$ can be controlled by the “write” plus which was applied before the measurements even at the same “read”gate voltage.ltage.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.212-216
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• 1997

A new metal tip fabrication process for low voltage operation is reported in this paper. The key element of the fabrication process is that isotropic silicon etching and oxidation process used in silicon tip fabrication is utilized for gate hole size reduction and gate oxide layer. A metal FEA with 625 tips was fabricated in order to demonstrate the validity of the new process and submicron gate apertures were successfully obtained from originally 1.7$\mu\textrm{m}$ diameter mask. The emission current above noise level was observed at the gate bias of 50V. The required gate voltage to obtain the anode current of 0.1${\mu}\textrm{A}$/tip was 74V and the emission current was stable above 2${\mu}\textrm{A}$/tip without any disruption. The local field conversion factor and the emitting area were calculated as 7.981${\times}$10\ulcornercm\ulcorner and 3.2${\times}$10\ulcorner$\textrm{cm}^2$/tip, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.2
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• pp.104-110
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• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.224-227
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• 1995

The micro-patterning by a Bow energy FIB whish has been conventionally utilized far mask-repairing was investigated. Amorphous Se$\_$75/Gee$\_$25/ resist irradiated by 9[keV]-defocused Ga$\^$+/ ion beam(∼10$\^$15/[ions/$\textrm{cm}^2$]) resulted in increasing the optical absorption, which was also observed also in the film exposed by an optical dose of 4.5${\times}$10$\^$20/[photons/$\textrm{cm}^2$]. The ∼0.3[eV] edge shift for ion-irradiated film was about twice to that obtained for photo-exposed. These large shift could be estimated as due to an increase in disorder from the decrease in the sloop of the Urbach tail. For Ga$\^$+/ FIB irradiation with a relatively low energy, 30[keV] and above the amount of dose of 1.4${\times}$10$\^$16/[ions/$\textrm{cm}^2$], the irradiated region in a-Se$\_$75/Ge$\_$25/ resist was perfectly etched in acid solution for 10[sec], which is relatively a short development time. A contrast was about 2.5. In spite of the relatively low incident energy,∼0.225[$\mu\textrm{m}$] pattern was clearly obtained by the irradiation of a dose 6.5${\times}$10$\^$16/[ions/$\textrm{cm}^2$] and a scan diameter 0.2[$\mu\textrm{m}$], from which excellent results were expected fur incident energies above 50[keV] which was conventionally used in FIBL.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.20-21
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• 2008

Ferroelectric vinylidene fluoride-trifluoroethylene ($VF_2$-TrFE) copolymer films were directly deposited on degenerated Si ($n^+$, 0.002 $\Omega{\cdot}cm$) using by dip coating method. A 1 ~ 3 wt% diluted solution of purified vinylidene fluoride-trifluoroethylene ($VF_2$:TrFE=70:30) in a dimethylformamide (DMF) solvent were prepared and deposited on silicon wafers using dip coating method for 10 seconds. After Post-Annealing in a vacuum ambient at 100~200 $^{\circ}C$ for 60 min, upper aluminum electrodes were deposited by thermal evaporation through the shadow mask to complete the MFS structure. The ferroelectric $\beta$-phase peak of films, depending on the annealing temperature, started to show up around $125^{\circ}C$, and the intensity of the peak increased with increasing annealing temperature. Above $175^{\circ}C$, the peak started to decrease. The C-V characteristics were measured using a Precision LCR meter (HP 4284A) with frequency of 1MHz and a signal amplitude of 20 mV. The leakage-current versus electric-field characteristics was measured by mean of a pA meter/DC voltage source (HP 4140B).

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1968-1970
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• 1996

We investigate a surface-micromachined polysilicon microgyroscope, whose resonant frequencies are electrostatically-tunable after fabrication. The microgyroscope with two oscillation nudes has been designed so that the resonant frequency in the sensing mode is higher than that in the actuating mode. The microgyroscope has been fabricated by a 4-mask surface-micrormachining process, including the deep RIE of a $6{\mu}m$-thick LPCVD polycrystalline silicon layer. The resonant frequency in the sensing mode has been lowered to that in actuating mode through the adjustment of an inter-plate bias voltage; thereby achieving a frequency matching at 5.8kHz under the bias voltage of 2V in a reduced pressure of 0.1torr. For an input angular rate of $50^{\circ}/sec$, an output signal of 20mV has been measured from the tuned microgyroscope under an AC drive voltage of 2V with a DC bias voltage of 3V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.7
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• pp.784-790
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• 2012

In this paper, an all-digital CMOS ultra-wideband(UWB) pulse generator for high band(6~10 GHz) frequency range is presented. The pulse generator is designed and implemented with extremely low power and low complexity. It is designed to meet the FCC spectral mask requirement by using Gaussian pulse shaping circuit and control the center frequency by using CMOS delay line with shunt capacitor. Measurement results show that the center frequency can be controlled from 4.5 GHz to 7.5 GHz and pulse width is 1.5 ns and pulse amplitude is 310 mV peak to peak at 10 MHz pulse repetition frequency(PRF). The circuit is implemented in 0.13 um CMOS process with a core area of only $182{\times}65um^2$ and dissipates the average power of 11.4 mW at an output buffer with 1.5-V supply voltage. However, the core consumes only 0.26 mW except for output buffer.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.48-57
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• 2020

MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single poly EEPROM cells have a large cell size. In this paper, a 110nm MTP cell using a vertical PIP capacitor is proposed. The erase operation of the proposed MTP cell uses FN tunneling between FG and EG, and the program operation uses CHEI injection method, which reduces the MTP cell size to 1.09㎛2 by sharing the PW of the MTP cell array. Meanwhile, MTP memory IP required for applications such as USB type-C needs to operate over a wide voltage range of 2.5V to 5.5V. However, the pumping current of the VPP charge pump is the lowest when the VCC voltage is the minimum 2.5V, while the ripple voltage is large when the VCC voltage is 5.5V. Therefore, in this paper, the VPP ripple voltage is reduced to within 0.19V through SPICE simulation because the pumping current is suppressed to 474.6㎂ even when VCC is increased by controlling the number of charge pumps turned on by using the VCC detector circuit.