• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.95-103
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• 2011

This paper proposes a 6b 1.2 GS/s 47.8 mW 0.17 $mm^2$ 65 nm CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 $V_{p-p}$ at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 nm CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 dB and a maximum SFDR of 44.7 dB at 1.2 GS/s. The ADC with an active die area of 0.17 $mm^2$ consumes 47.8 mW at 1.2 V and 1.2 GS/s.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• Transactions of the Korean Society of Mechanical Engineers
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• v.10 no.1
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• pp.110-120
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• 1986

45.deg. corss jet flow, at the mixing of two jet flows, was experimentally studied. For this study, only the statistical turbulent characteristics and high order moments will be analysed by on-line computer system (hot-wire anemometer system, dynamic analyser and computer system, plotting and printing system). Since mean velocity distributions, intensities of turbulence, Reynolds stresses, correlation coefficients, and other general results were already studied and presented. One dimensional probability density distributions of u', v', and w' were analysed comparing with Gaussian curve, which showed skew and flat tendency according to the Y and Z directions. For the analysis of the joint flow of turublent components, the joint probability density distributions were examined. The fagures were drawn so as to be read joint probabilities, joint probability densities, fluctuating velocities u', v', and w'. For further detailed examination of the variations of skewness and flatness phenomena, iso-joint probability density contours obtained from the profiles of the joint probability density distributions were studied. According to the displacement of positions from the center of the mixing flow and the directions, the flatness and skewness factors were increased.

• Journal of IKEEE
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• v.26 no.4
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• pp.659-670
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• 2022

An 830-Mb/s/pin transceiver for a controller supporting ×32 LPDDR2 memory is designed. The transmitter consists of eight unit circuits has an impedance in the range of 34Ω ∽ 240Ω, and its impedance is controlled by an impedance correction circuit. The transmitted DQS signal has a phase shifted by 90° compared to the DQ signals. In the receive operation, the read time calibration is performed by per-pin skew calibration and clock-domain crossing within a byte. The implemented transceiver for the LPDDR2 memory controller is designed by using a 55-nm process using a 1.2V supply voltage and has a maximum signal transmission rate of 830 Mb/s/pin. The area and power consumption of each lane are 0.664 mm² and 22.3 mW, respectively.

• Journal of the Optical Society of Korea
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• v.19 no.2
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• pp.136-143
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• 2015

Image deblurring by a deconvolution method requires accurate knowledge of the blur kernel. Existing point spread function (PSF) models in the literature corresponding to lens aberrations and defocus are either parameterized and spatially invariant or spatially varying but discretely defined. In this paper, a parameterized model is developed and presented for a PSF which is spatially varying due to lens aberrations and defocus in an imaging system. The model is established from the Seidel third-order aberration coefficient and the Hu moment. A skew normal Gauss model is selected for parameterized PSF geometry structure. The accuracy of the model is demonstrated with simulations and measurements for a defocused infrared camera and a single spherical lens digital camera. Compared with optical software Code V, the visual results of two optical systems validate our analysis and proposed method in size, shape and direction. Quantitative evaluation results reveal the excellent accuracy of the blur kernel model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.18-24
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• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• Journal of the Society of Naval Architects of Korea
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• v.28 no.2
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• pp.52-68
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• 1991

A new propeller series is developed using the newly developed blade section(KH18 section) which behaves better cavitation characteristics and higher lift-drag ratio at wide range of angle-of-attack. The pitch and camber distributions are disigned in order to have the same radial and chordwise loading distribution with the selected circumferentially averaged wake input. Since the geometries of the series propeller, such as chord length, thickness, skew and rate distribations, are selected by regression of the recent full scale propeller geometric data, the performance prediction of a propeller at preliminary design stage can be mure realistic. Number of blades of the series propellers is 4 and the expanded blade area ratios are 0.3, 0.45, 0.6 and 0.75. Mean pitch ratios are selected as 0.5, 0.65, 0.8, 0.75 and 1.1 for each expanded area ratio. The new propeller series is composed of 20 propellers and is named as KD(KRISO-DAEWOO) propeller series. Propeller open water tests are performed at the experimental towing tank, and the cavitation observation tests and fluctuating pressure measurements are carried out at the cavitation tunnel of KRISO. $B_{P}-\delta$ curves, which can be used to select the optimum propeller diameter at the preliminary design stage, are derived from a regression analysis of the propeller often water test results. The KD-cavitation chart is derived from the cavitation observation test results by choosing the local maximum lift coefficient and the local cavitation number as parameters. The caviy extent of a propeller can be predicted more accurately by using the KD-cavitation chart at a preliminary design stage, since it is derived from the results of the cavitation observation tests in the selected ship's wake, whereas the existing cavitation charts, such as the Burrill's cavitation chart, are derived from the test results in uniform flow.