• Electrical & Electronic Materials
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• v.6 no.2
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• pp.152-160
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• 1993

MNOS 구조에서 23.angs.의 얇은 산화막을 성장한 후 LPCVD방법으로 S $i_{3}$ $N_{4}$막을 각각 530.angs., 1000.angs. 두께로 달리 증착했을때 비휘발성 기억동작에 미치는 전하주입 및 기억유지 특성을 자동 .DELTA. $V_{FB}$ 측정 시스템을 제작하여 측정하였다. 전하주입 측정은 펄스전압 인가전의 초기 플랫밴드전압 0V.+-.10mV, 펄스폭 100ms 이내로 설정하고 단일 펄스전압을 인가하였다. 기억유지특성은 기억트랩에 전하를 포획시킨 직후 $V_{FB}$ 유지와 0V로 유지한 상태에서 $10^{4}$sec까지 측정하였다. 본 논문에서 유도된 산화막 전계에 대한 터넬확률을 적용한 전하주입 이론식은 실험결과와 잘 일치하였으며 본 해석방법으로 직접기억트랩밀도와 이탈진도수를 동시에 평가할 수 있었다. 기억트랩의 포획전하는 실리콘쪽으로의 역 터넬링으로 인한 조기감쇠가 컸으며 $V_{FB}$ 유지인 상태가 초기 감쇠율이 0V로 유지한 경우 보다 낮았다. 그리고 기억유지특성은 S $i_{3}$ $N_{4}$막의 두께보다 기억트랩밀도의 의존성이 크며 S $i_{3}$ $N_{4}$막두께의 축소로 기록전압을 저전압화시킬 수 있음을 알 수 있었다.

• Transactions on Electrical and Electronic Materials
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• v.14 no.5
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• pp.250-253
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• 2013

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of $N_2$ ion implantation ($N_2$ I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage ($V_{\tau}$) of 0.13 V, and a higher $g_{m.max}$ of 18.6 ${\mu}A/V$ and mobility of 27.02 $cm^2/Vs$ than the conventional and $N_2$ I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and $N_2$ I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.464-467
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• 2004

An uncooled infrared sensor has been prepared with sputtering, plasma ash, ICP, and PECVD on a Si wafer In order to analyze the resistance characteristics with the bridge length in the infrared sensor, three samples were prepared with lengths of 0 (no bridge), 15 (short bridge), and 29 urn (long bridge), respectively. I-V curves were measured for their resistance characteristics and EPMA for the dopping concentration of the amorphous Si. The phosphorus concentration was about 4 % and the resistance was increased with the bridge length. The bridge length of cantilever is very important factor for improvement of the efficiency in an infrared sensor.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.60-61
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• 2007

In this paper, the p-channel poly Si thin-film transistors (Poly-Si TFT's) using formed by solid phase crystallization (SPC) on glass substrate were fabricated. And we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's to indicate non-volatile memory (NVM) effect. Poly-Si TFT is investigated by measuring the electrical properties of poly-Si films, such as I-V characteristics, on/off current ratio. NVM characteristics is showed by measuring the threshold voltage change of TFT through I-V characteristics.

• Journal of the Korean Applied Science and Technology
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• v.15 no.3
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• pp.85-90
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• 1998

In this study, organic electroluminescent devices(OELD) with a structure of a glass $substrate/ITO/TPD/Tb(ACAC)_3(Phen-Cl)/Alq_3/Al$ was fabricated by vacuum evaporation method, where Tb complex was known to have green light emitting property. Electroluminescent(EL) and I-V characteristics of this structure were investigated. This triple-layer structure shows the green EL spectrum at the wavelwngth of 546nm, which is almost the same as the PL spectrum of $Pb(ACAC)_3(Phen_Cl)$. It was found in current-voltage(I-V) characteristics of the devices that the operating voltage was about 12V.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1373-1376
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• 1998

Electroluminescent(EL) devices based on organic materials have been of great interest due to their possible applications for large-area flat-panel displays. They are attractive because of their capability of multicolor emission, and low operation voltage. In this study, glass substrate/ITO/TPD/$Eu(TTA)_3(phen)/Alq_3/Al$ structures were fabricated by evaporation method, where aromatic diamine(TPD) were used as a hole transporting material, $Eu(TTA)_3(phen)$ as an emitting material, and tris(8-hydroxyquinoline)Aluminum ($Alq_3$) as an electron transporting layer. Electroluminescent(EL) and I-V characteristics of $Eu(TTA)_3(phen)$ with a variety thickness was investigated. This structure shows the red EL spectrum, which is almost the same as the PL spectrum of $Eu(TTA)_3(phen)$. I-V characteristics of this structure show that turn-on voltage was 9V and current density of $0.01A/cm^2$ at a dc drive voltage of 9V. Details on the explanation of electrical transport phenomena of these structures with I-V characteristics using the trapped-charge-limited current model will be discussed.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1332_1333
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• 2009

The electrical properties of an inorganic/organic heterojunction has been investigated by spin coating the p-type polymer poly(3,4 ethylenedioxythiophene) : poly(styrenesulfonate) (PEDOT:PSS) on an n-type gallium doping zinc oxide (GZO) film. Current-voltage (I-V) characteristics of the fabricated heterojunction diodes have a good rectifying characteristics. The barrier height is calculated 0.8 eV.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.882-889
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• 2011

In this study, we have investigated the effects of Co doping on I-V curves, bulk trap levels and grain boundary characteristics of ZnO-$Bi_2O_3$ (ZB) varistor. From I-V characteristics the nonlinear coefficient (a) and the grain boundary resistivity (${\rho}_{gb}$) decreased as 32${\rightarrow}$22 and 18.4${\rightarrow}0.6{\times}10^9{\Omega}cm$ with sintering temperature (900~1,300$^{\circ}C$), respectively. Admittance spectra and dielectric functions show two bulk traps of zinc interstitial, $Zn_i^{{\cdot}{\cdot}}$(0.16~0.18 eV) and oxygen vacancy, $V_o^{{\cdot}}$ (0.28~0.33 eV). The barrier of grain boundaries in ZBCo (ZnO-$Bi_2O_3-Co_3O_4$) could be electrochemically single type. However, its thermal stability was slightly disturbed by ambient oxygen because the apparent activation energy of grain boundaries was changed from 0.93 eV at the 460~580 K to 1.13 eV at the 620~700 K. It is revealed that Co dopant in ZB reduced the heterogeneity of the barrier in grain boundaries and stabilized the barrier against the ambient temperature.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.6
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• pp.229-235
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• 2002

This paper presents the fabrication of polycrystalline thin film transistor(TFT) using sequential lateral solidification(SLS) of amorphous silicon. The fabricated SLS TFT showed high Performance suitable for active matrix liquid crystal display(AMLCD). The SLS process involves (1) a complete melting of selected area via irradiation through a patterned mask, and (2) a precisely controlled pulse translation of the sample with respect to the mask over a distance shorter than the super lateral growth(SLG) distance so that lateral growth extended over a number of iterative steps. The SLS experiment was performed with 550$\AA$ a-Si using 308nm XeCl laser having $2\mu\textrm{m}$ width. Irradiated laser energy density is 310mJ/$\textrm{cm}^2$ and pulse duration time was 25ns. The translation distance was 0.6$\mu$m/pulse, 0.8$\mu$m/pulse respectively. As a result, a directly solidified grain was obtained. Thin film transistors (TFTs) were fabricated on the poly-Si film made by SLS process. The characteristics of fabricated SLS p -type poly-Si TFT device with 2$\mu\textrm{m}$ channel width and 2$\mu\textrm{m}$ channel length showed the mobility of 115.5$\textrm{cm}^2$/V.s, the threshold voltage of -1.78V, subthreshold slope of 0.29V/dec, $I_{off}$ current of 7$\times$10$^{-l4}$A at $V_{DS}$ =-0.1V and $I_{on}$ / $I_{off}$ ratio of 2.4$\times$10$^{7}$ at $V_{DS}$ =-0.1V. As a result, SLS TFT showed superior characteristics to conventional poly-Si TFTs with identical geometry.y.y.y.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.1
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• pp.51-56
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• 2014

PV cell modeling is necessary both for software and hardware simulators in analyzing and testing the performance of PV generation systems. Unique I-V curve of a PV cell identifies its own characteristics by electrical equivalent model that is composed of diode constants ($I_o$, $v_t$), photo-generated current ($I_{ph}$), series resistance ($R_s$), and shunt resistance ($R_{sh}$). Photo-generated current can be easily estimated since it is proportional to irradiation level. However, other electrical parameters should be solved from the manufacturer's data sheet that is consisted with three remarkable operating points such as open circuit voltage ($V_{oc}$), short circuit current ($I_{sc}$), and maximum power voltage/current ($V_{MPP}/I_{MPP}$). This paper explains and analyzes mathematical process of a novel PV cell modeling algorithm that was proposed by the authors with the name of "K-algorithm".