• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.630-637
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• 2003

In this paper, a DBM(double balanced mixer) of 2 GHz is implemented on FR4(h=1.6mm, ${\epsilon}_r=4.6$) substrate. The structure of double balanced mixer requires, in general, two talons and a quad diode. For balun, a novel planar balun using microstrip to CPS(Coplanar Strip) is suggested and designed. The suggested balun shows the phase imbalance of $180^{\circ}{\pm}1.5^{\circ}$ and the amplitude imbalance of ${\pm}0.2 dB$ for 1.5 to 2.5 GHz. Using the balun, DBM is successfully implemented, and the measured conversion loss of up/down converter show about 6 dB over the bandwidth. The balun may be applicable for MMIC(Monolithic Microwave Integrated Circuit) DBM with the process supporting backside via though more study.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.608-618
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• 2004

In this paper, modifying the diode star double balanced mixer of Maas, a novel resistive 60 GHz pHEMT MMIC star mixer is suggested. Due to star configuration, troublesome IF balun for ring configuration FET mixer is not necessary. In addition, the sysematic design method of dual balun through EM simulation is suggested rather than the design by inspection as Maas. The mixer circuit is fabricated as MMIC on CPW base using 0.1 um GaAs pHEMT Library of MINT in Dongguk University. The size is 1.5 ${\times}$ 1.5 $\textrm{mm}^2$ and its performance is adjustable by DC supply. It can be operated as both up and down converters and it shows the conversion loss of about 13∼18 ㏈ over the full V-band frequencies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.1
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• pp.44-50
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• 2004

In this paper, a DBM(Doubly Balanced Mixer) of 2 GHz is implemented on FR4 substrate. The structure of doubly balanced mixer requires, in general, two batons and a quad diode. For balun, a novel planar balun using microstrip to CPS is suggested and designed. The suggested balun shows the phase imbalance of 180$^{\circ}$${\pm}$ 1.5$^{\circ}$and the amplitude imbalance of ${\pm}$ 0.2 ㏈ for 1.5 to 2.5 GHz. Using the balun, DBM is succesfully implemented, and the measured conversion loss of up/down converter show about 6 ㏈ over the bandwidth. The balun may be applicable for MMIC DBM with the process supporting backside via thourgh more study.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1009-1014
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• 2012

This paper has proposed a 2,500 MHz ~ 2,570 MHz 0.13-${\mu}m$ CMOS RF front-end transmitter for LTE-Advanced systems. The proposed RF front-end transmitter is composed of a quadrature up-conversion mixer and a driver amplifier. The measurement results show the maximum output power level is +6 dBm and the suppression ratio for the image sideband and LO leakage are better than -40 dBc respectively. The fabricated chip consumes 36 mA from a 1.2 V supply voltage.

• ETRI Journal
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• v.36 no.6
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• pp.924-930
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• 2014

This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.1 no.1
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• pp.23-31
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• 1976

When Television signal of VHF and UHF channel is retransmitted at the relay system with 6MHz Bandwidth including video and aural signals, the image is often affected with the unnatural changes of output amplitude frequency response within ttle region of dual sideband near to the carrier frequency. These phenomena are caused by the unnecessary lower sideband due to the spurious emission at the local oscillator, the nonlinear distortion in the linear amplifier, the intermoudulation distortion with the components of neighboring signal, the AM-PM conversion, and the envelope delay distortion. From the output characteristics, considering above results, the chief cause is caused by nonlinear response and has an effect on the bias states. Finally, it is confirmed that the effects on neighboring signal appear high in case of Down conversion than Up conversion and obtained the method for reducing the effects on the system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1571-1577
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• 1994

This paper is designed and implemented mixer of 12GHz/14GHz as up-conversion. Observation that harmonics and intermodulation power level varied by two signal power level and bias obtained operation points of mixer. Finally, optimum operation points shows that $P_{RF}$(radio signal frequency power level). $P_{LO}$(local oscillation power level) is below -30[dBm], -2[dBm] respectively. Simultaneously $V_{DS}$ is 2.7[V]and $V_{GS}$ is -0.2[V].

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2006.07a
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• pp.717-717
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• 2006

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.323-323
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• 2004

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2589-2591
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• 2002

송수신기의 방식에는 직접변환 방식과 기저대역 신호와 LO(Local Oscillator)를 혼합하여 interpolation 기법을 사용하여 중간 주파수 단계까지 up conversion을 하고 두 번째 LO와 IF신호를 혼합하여 RF신호로 변환하여 송신하는 헤테로다인 방식이 존재한다. 본 논문에서는 이런 송수신기 방식 중에서 헤테로다인 방식을 적용하여 QPSK에서의 digital up /down converter를 Simulink 환경에서 설계 및 구현하였다. Up converter는 4배의 interpolation 필터와 4단짜리 cascaded integrate-comb(CIC)필터를 사용하여 입력데이터의 샘플 레이트를 클럭 레이트까지 증가시켰으며, numerically controlled oscillator (NCO)와 mixer를 사용하여 신호를 변조하였다. Down converter의 구조는 up converter와 동일하며 단지 up converter의 반대순서로 구성되어있다. 이런 모든 과정을 Simulink를 이용한 시뮬레이션과 스펙트럼 분석기를 사용하여 검증해 보았다.