• Title/Summary/Keyword: Ultra-WideBand(UWB)

Search Result 310, Processing Time 0.027 seconds

Performance Analysis for Spatial Multiplexing MIMO in MB-OFDM UWB Receivers (MB-OFDM UWB 시스템에서 공간 다중화 MIMO 수신기의 성능 분석)

  • Suh, Jung-Won;Kwon, Yang-Soo;Kim, Seok-Hyeon;Chung, Jea-Hak
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.33 no.2A
    • /
    • pp.121-129
    • /
    • 2008
  • This paper presents the spatial multiplexing MIMO system to increase data rate to double in MB-OFDM UWB system, which is ECMA standards, and compares BER performance of various receiver structures. The complexity and BER performance of various types of spatial multiplexing receivers are compared and analyzed using diagonal and horizontal encoding techniques for $2{\times}2$\;and\;2{\times}3$ antennas systems. Computer simulations exhibit that $2{\times}2$ MML and $2{\times}3$ ZF method show better BER performance than that of SISO system with simple complexity.

A Low Power Single-End IR-UWB CMOS Receiver for 3~5 GHz Band Application (3~5 GHz 광대역 저전력 Single-Ended IR-UWB CMOS 수신기)

  • Ha, Min-Cheol;Park, Byung-Jun;Park, Young-Jin;Eo, Yun-Seong
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.20 no.7
    • /
    • pp.657-663
    • /
    • 2009
  • A fully integrated single ended IR-UWB receiver is implemented using 0.18 ${\mu}m$ CMOS technology. The UWB receiver adopts the non-coherent architecture, which simplifies the RF architecture and reduces power consumption. The receiver consists of single-ended 2-stage LNAs, S2D, envelope detector, VGA, and comparator. The measured results show that sensitivity is -80.8 dBm at 1 Mbps and BER of $10^{-3}$. The receiver uses no external balun and the chip size is only $1.8{\times}0.9$ mm. The consumed current is very low with 13 mA at 1.8 V supply and the energy per bit performance is 23.4 nJ/bit.

An improvement algorithm for localization using adjacent node and distance variation analysis techniques in a ship (근접노드와 거리변화량분석기법을 이용한 선내 위치인식 개선 알고리즘)

  • Seong, Ju-Hyeon;Lim, Tae-Woo;Kim, Jong-Su;Park, Sang-Gug;Seo, Dong-Hoan
    • Journal of Advanced Marine Engineering and Technology
    • /
    • v.37 no.2
    • /
    • pp.213-219
    • /
    • 2013
  • Recently, with the rapid advancement in information and communication technology, indoor location-based services(LBSs) that require precise position tracking have been actively studied with outdoor-LBS using GPS. However, in case of a ship which consists of steel structure, it is difficult to measure a precise localization due to significant ranging error by the diffraction and refraction of radio waves. In order to reduce location measurement errors that occur in these indoor environments, this paper presents distance compensation algorithms that are suitable for a narrow passage such as ship corridors without any additional sensors by using UWB(Ultra-wide-band), which is robust to multi-path and has an error in the range of a few centimeters in free space. These improvement methods are that Pythagorean theory and adjacent node technique are used to solve the distance error due to the node deployment and distance variation analysis technique is applied to reduce the ranging errors which are significantly fluctuated in the corner section. The experimental results show that the number of nodes and the distance error are reduced to 66% and 57.41%, respectively, compared with conventional CSS(Chirp spread spectrum) method.

Ultra-Wideband Band Pass Filter with Controllable Dual Notched Bands Using the CRLH Stubs (CRLH-Stub를 이용한 이중대역 저지 초광대역 대역통과 여파기)

  • Jung, Seung-Back;Yang, Seung-In
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.49 no.7
    • /
    • pp.65-70
    • /
    • 2012
  • In this paper, a compact UWB (Ultra Wideband) BPF(Band-Pass Filter) with dual notched bands is proposed using a hybrid Composited Right-Left Handed (CRLH) and Defected Ground Structure (DGS). To avoid the interferences such as Wireless LAN (Center frequency: 2.4GHz and 5.8GHz), the CRLH is employed to obtain the dual notched bands and the DGS is used to obtain the wide stop-band above the pass-band. The fabricated filter has good performance and has more than 30dB rejection at the center frequency of 2.4 GHz and 5.8GHz. The dual notched bands are easily movable by changing the CRLH parameter. Also the insertion loss is less than 0.4dB in the lower pass-band and 0.7dB in the upper pass-band, and it has small group delay variation less than 0.6ns. The size of the fabricated filter is very compact (17mm*17mm).

Design for Trapezoidal Planar UWB Antenna Using Symmetry Meander Feedline (대칭 미앤더 급전 선로를 이용한 사다리꼴 평면 UWB 안테나 설계)

  • Kim, Tae-Geun;Min, Kyeong-Sik
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.20 no.8
    • /
    • pp.739-745
    • /
    • 2009
  • This paper presents a design for trapezoidal planar UWB(Ultra Wide-band) antenna using symmetry meander line to realize broad bandwidth at low frequency region. The size of proposed design antenna is $15.5{\times}21{\times}1.6mm^3$ and dielectric substrate considered in design has 4.4 of relative permittivity. The calculated bandwidth is from 1.31 GHz to 10.83 GHz and the measured return loss is 1.5 GHz to 10.6 GHz at -10 dB below, and satisfies with the UWB antenna's bandwidth. The simulated and measured radiation patterns show fine agreement with each other at each frequency.

A 3 ~ 5 GHz CMOS UWB Radar Chip for Surveillance and Biometric Applications

  • Lee, Seung-Jun;Ha, Jong-Ok;Jung, Seung-Hwan;Yoo, Hyun-Jin;Chun, Young-Hoon;Kim, Wan-Sik;Lee, Noh-Bok;Eo, Yun-Seong
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.11 no.4
    • /
    • pp.238-246
    • /
    • 2011
  • A 3-5 GHz UWB radar chip in 0.13 ${\mu}m$ CMOS process is presented in this paper. The UWB radar transceiver for surveillance and biometric applications adopts the equivalent time sampling architecture and 4-channel time interleaved samplers to relax the impractical sampling frequency and enhance the overall scanning time. The RF front end (RFFE) includes the wideband LNA and 4-way RF power splitter, and the analog signal processing part consists of the high speed track & hold (T&H) / sample & hold (S&H) and integrator. The interleaved timing clocks are generated using a delay locked loop. The UWB transmitter employs the digitally synthesized topology. The measured NF of RFFE is 9.5 dB in 3-5 GHz. And DLL timing resolution is 50 ps. The measured spectrum of UWB transmitter shows the center frequency within 3-5 GHz satisfying the FCC spectrum mask. The power consumption of receiver and transmitter are 106.5 mW and 57 mW at 1.5 V supply, respectively.

Design and Comparison of the Fast-Hopping Frequency Synthesizers for MB-OFDM UWB Systems (MB-OFDM 방식의 UWB 시스템을 위한 Fast-Hopping 주파수 합성기의 유형별 설계 및 비교)

  • Lee, Jae-Kyoung;Park, Joon-Kyu;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.10 no.12
    • /
    • pp.2264-2270
    • /
    • 2006
  • This paper describes fast-hewing frequency synthesizers for multi-band OFDM(MB-OFDM) ultra-wide band(UWB) systems. Three different structures in generating 3 center frequencies(3432MHz, 3960MHz, 4488MHz) are designed and compared. The first structure generates 3 center frequencies using only one PLL operating at 4224MHz, and the second uses three PLLs operating at corresponding center frequencies. The proposed third structure employes two PLLs operating at 3960MHz and 528MHz. Simulation results using 0.18um RF CMOS process parameters show that the third structure exhibits boner characteristics in spur, area and current consumption than the other structures. The band switching time of the proposed synthesizer is less than 1.In and the spur is less than -36dBc. The synthesizer consumes 22mA from a 1.8V supply.

Design and Analysis of Ultra-WideBand(UWB) Microstrip patch Dipole Antenna (초광대역(UWB) 마이크로스트립 패치 다이폴 안테나 설계 및 분석)

  • Chang Soo-Keun;Ko Kwang Cheol
    • Proceedings of the IEEK Conference
    • /
    • 2004.06a
    • /
    • pp.193-196
    • /
    • 2004
  • This paper have a whole azimuth Omni-directional radiation pattern and will become the good radiation efficiency for applies in the steeve antenna and form which is the appearance. We contain by whole course of actual implement model to antenna design. And we will confirm the efficiency the analysis of the antenna to design and through a simulated experiment according to the implementation Ideal characteristic of the antenna to be used between 3.1 and 10.6 GHz of UWB.

  • PDF

The design of parallel Viterbi decoder for UWB system (UWB system 구현을 위한 병렬 구조 비터비 복호기 설계)

  • Lee Kyu Sun;Yoon Sang Hun;Chong Jong-Wha
    • Proceedings of the IEEK Conference
    • /
    • 2004.06a
    • /
    • pp.289-292
    • /
    • 2004
  • In this paper, we propose parallel Viterbi decoders applied to UWB(Ultra Wide Band). In consideration of power dissipation and ease of design, we design the architecture, using 132MHz clock instead of 528MHz clock in Baseband. Because Deinterleaver writes and reads the transmitted data per 6Ncbps(The number of coded bits per symbol). using the difference between the number of sampling clock per symbol and the number of coded bits per symbol, we reduce performance degradation of parallel Viterbi decoders. In comparison with using 528MHz clock, the result is little difference.

  • PDF

A Study on the Design of FFT Architecture for Ultra-Wide Band OFDM Communication System (UWB OFDM 통신 시스템 용 FFT(Fast Fourier Transform) 설계에 관한 연구)

  • Park Kye-Wan;Yoon Sang-hun;Chong Jong-Wha
    • Proceedings of the IEEK Conference
    • /
    • 2004.06a
    • /
    • pp.309-312
    • /
    • 2004
  • This paper proposes the architecture of UWB OFDM communication system. More high data rate is requested in the 128-point FFT/IFFT of the UWB OFDM communication system than the conventional communication systems. So, the proposed architecture uses pipeline and parallel architecture. For a highly efficient architecture, the optimal clipping power and the input quantization bits are found in simulation. The hardware complexity of the proposed architecture is presented is consideration of Adder, Register and Complex Multiplier.

  • PDF