• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.55-60
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• 2017

This paper is proposed on the transmit Method Finger-Printer Scanning of Mutual Capacitance Touch Screen Panel Using Differential Pulse for improving the security of computer information. This system is composed of differential pulse generator and Ring-Counter, also Supply voltage is 5V. this system generates the Pulse wave which is composed of In-Phase and Out of Phase at 1MHz while period of 2m/s. it is designed and be able to operate four channels. overall power consumption is approximately 78.08nW. This prototype is implemented in 0.25um CMOS Process and Chip area is $870um{\times}880um$.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.7
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• pp.659-664
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• 2016

In this paper, we suggest operational trans-conductance amplifier(OTA) for current-mode FIR filter that can be used in a digital circuit system requiring high operating frequency and low power consumption. The current-mode signal processing is one of the very innovative design method for a low power consumption system with high operating frequency because it shows a constant power regardless of frequency. From the simulation result using 0.35um CMOS process, when Vdd is 2V, it is confirmed that the proposed circuit showed the dynamic range of the about 1V, about 50% of supply voltage and output current swing of about 0~200uA. Also, the power consumption was evaluated with about 21uW and the active size for an integration was measured with $71um{\times}166um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.361-364
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• 2013

Since the non-overlapping gate driver used in conventional DC-DC boost converters generates fixed dead-times, the converters suffer from the body-diode conduction loss or the charge-sharing loss. A adaptive control method has been proposed to reduce these loses. In this method, however, occurrence of and overlapping time of two power transistors in CCM results in reduction of efficiency. In this paper, to overcome this problem a new adaptive control method in proposed, and a DC-DC boost converter with the proposed adaptive control and power switching has been designed in a 0.35um CMOS process. The designed converter outputs 3.3V from a input voltage of 2.5V. The switching frequency is 500kHz and the maximum power efficiency is 95.3% at a load current 150mA. The designed chip area is $1720um{\times}1280um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.412-415
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• 2015

This paper presents a MPPT(Maximum Power Point Tracking) control CMOS interface circuit for vibration energy harvesting. The proposed circuit consists of an AC-DC converter, MPPT Controller, DC-DC boost converter and PMU(Power Management Unit). The AC-DC converter rectifies the AC signals from vibration devices(PZT). MPPT controller is employed to harvest the maximum power from the PZT and increase efficiency of overall system. The DC-DC boost converter generates a boosted and regulated output at a predefined level and provides energy to load using PMU. A full-wave rectifier using active diodes is used as the AC-DC converter for high efficiency, and a schottky diode type DC-DC boost converter is used for a simple control circuitry. The proposed circuit has been designed in a 0.35um CMOS process. The chip area is $950um{\times}920um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.484-487
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• 2015

This paper describes a dual-input battery charger with MPPT control using photovoltaic and piezoelectric energy. Each energy is harvested from photovoltaic cells and piezoelectric cells and is stored to each capacitor. The battery voltage is boosted by charger block and two energy sources are used as input to charge battery capacitor. A DC-DC boost converter is designed to boost the battery voltage, and inductor sharing technique is employed such that only one inductor is required. The time division ratio for piezoelectric cell and photovoltaic cell is set to 8:1. The proposed circuit is designed in a 0.35um CMOS process technology. The condition of battery capacitor is managed by battery management block and the battery voltage can be boosted up to 3V. The maximum efficiency of the designed entire system is 88.56%, and the chip area including pads is $1230um{\times}1330um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.411-414
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• 2011

This paper describes a tripple-mode DC-DC buck converter with DPSS Fucntion. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(80mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~80mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 97.02% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is $1465um{\times}895um$ including pads.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.569-572
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• 2014

This paper presents a CMOS switched-capacitor interface circuit for MEMS capacitive sensors. It consist of a capacitance to voltage converter(CVC), a second-order ${\Sigma}{\Delta}$ modulator, and a comparator. A bias circuit is also designed to supply constant bias voltages and currents. This circuit employes the correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques to reduce low-frequency noise and offset. The designed CVC has a sensitivity of 20.53mV/fF and linearity errors less than 0.036%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 5% as the input voltage amplitude increases by 100mV. The designed interface circuit shows linearity errors less than 0.13%, and the current consumption is 0.73mA. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V. The size of the designed chip including PADs is $1117um{\times}983um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.520-523
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• 2016

This paper describes a DC-DC converter with MPPT control for thermoelectric energy harvesting. The designed circuit converts low voltage harvested from a thermoelectric generator into higher voltage for powering a load. A start-up circuit supplies VDD to a controller, and the controller turns on and off a NMOS switch of a main-boost converter. The converter supplies the boosted voltage to the load through the switch operation. Bulk-driven comparators can do the comparison under low voltage condition and are used for voltage regulation. Also, bulk-driven comparators raise system's efficiency. A peak conversion efficiency of 76% is achieved. The proposed circuit is designed in a 0.35um CMOS technology and its functionality has been verified through simulations. The designed chip occupies $933um{\times}769um$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.267-270
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• 2014

This paper presents a CMOS interface circuit for vibration energy harvesting. The proposed circuit consists of an AC-DC converter and a DC-DC boost converter. The AC-DC converter rectifies the AC signals from vibration devices(PZT), and the DC-DC boost converter generates a boosted and regulated output at a predefined level. A full-wave rectifier using active diodes is used as the AC-DC converter for high efficiency, and a schottky diode type DC-DC boost converter is used for a simple control circuitry. A MPPT(Maximum Power Point Tracking) control is also employed to harvest the maximum power from the PZT. The proposed circuit has been designed in a 0.35um CMOS process. The chip area is $530um{\times}325um$. Simulation results shows that the maximum efficiencies of the AC-DC converter and DC-DC boost converter are 97.7% and 89.2%, respectively. The maximum efficiency of the entire system is 87.2%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.