• E2M - 전기 전자와 첨단 소재
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• 제9권4호
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• pp.336-343
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• 1996

We have studied the preparation and the properties of $Ba_{1-x}$Sr$_{x}$TiO$_{3}$(BST) thin films by using the sol-gel method. Through the comparison of the effects of various solvents and additives in making solutions, we establish the production method of the stable solution which generates the high quality of BST film. We also set up the heat-treatment conditions for depositing the BST thin film through the TGA and XRD analyses. Through the comparison of the surface conditions of BST films deposited on Pt/Ta/SiO$_{2}$/Si and Pt/Ti/SiO$_{2}$/Si substrates, we find that Ta is more efficient diffusion barrier of Si than Ti so that Ta layer prevents the formation of hillocks. We fabricate the planar type capacitor and measure the dielectric properties of the BST thin film deposited on the Pt/Ta/SiO$_{2}$/Si substrate. Dielectric constant and dielectric loss tangent at 1V, 10kHz, and leakage current density at 3V of the BST thin film are 339, 0.052 and 13.3.mu.A/cm$^{2}$, respectively.ely.

• Transactions on Electrical and Electronic Materials
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• 제7권4호
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• pp.157-162
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• 2006

Chemical-mechanical polishing (CMP), one of the dominant technology for ULSI planarization, is used to flatten the micro electro-mechanical systems (MEMS) structures. The objective of this paper is to achieve good planarization of the deposited film and to improve deposition efficiency of subsequent layer structures by using surface-micromachining process in MEMS technology. Planarization characteristic of poly-Si film deposited on thin oxide layer with MEMS structures is evaluated with different slurries. Patterns used for this research have shapes of square, density, line, hole, pillar, and micro engine part. Advantages of CMP process for MEMS structures are observed respectively by using the test patterns with structures larger than 1 urn line width. Preliminary tests for material selectivity of poly-Si and oxide are conducted with two types of silica slurries: $ILD1300^{TM}\;and\;Nalco2371^{TM}$. And then, the experiments were conducted based on the pretest. A selectivity and pH adjustment of slurry affected largely step heights of MEMS structures. These results would be anticipated as an important bridge stone to manufacture MEMS CMP slurry.

• 한국진공학회지
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• 제7권4호
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• pp.368-373
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• 1998

초고집적 회로의 미세화에 따라 다층배선에서 기생저항(parasitic resistance)과 정전 용량의 증가는 RC시정수(time constant)의 증가로 인하여 소자의 동작속도를 제한하고 있 다. 이로 인하여 발생되는 배선지연의 문제를 해결하기 위하여 매우 낮은 유전상수를 갖는 층간 절연물질이 필요하다. 이러한 저유전상수 층간절연물질로서 현재 유기계 물질중의 하 나인 a-C:F이 주목받고 있는 물질이다. 본 연구에서는 ECRCVD를 이용하여 a-C:F박막과 Si기판사이의 밀착력을 향상시키기 위하여 a-C:H박막을 500$\AA$증착한 후 a-C:F을 증착전력 500W에서 원료가스의 유량비($C_2F_6, CH_4/(C_2F_6+CH_4)$))를 0~1.0까지 변화시키면서 상온에서 증착하 였다. a-C:F박막의 특성은 SEM, FT0IR, XPS, C-V meter와 AFM등을 이용하여 두께, 결 합상태, 유전상수, 표면형상 및 표면 거칠기를 관찰하였다. a-C:F박막에서 불소함량은 가스 유량비가 1.0일 경우에는 최대 약31at.%정도 검출되었으며, 가스 유량비가 증가됨에 따라 증 가하였다. 또한 유전상수는 a-C:H의 유전상수 $\varepsilon$=3.8에서 $\varepsilon$=2.35까지 감소하였다. 이는 영 구 쌍극자 모멘트가 1.5인 C-H결합은 감소하고 영구 쌍극자 모멘트가 0.6, 0.5인 CF, CF2결 합이 증가하였기 때문이다. 하지만 $400^{\circ}C$에서 질소분위기로 1시간 동안 furnace열처리 후에 가스유량비가 1.0인 a-C:F박막에서 불소의 함량이 감소하여 C-F결합이 줄어들었다. 이로 인하여 유전상수가 열처리전의 2.7에서 열처리후 3.2까지 상승하였다.

• E2M - 전기 전자와 첨단 소재
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• 제4권1호
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• pp.38-44
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• 1991

본 연구는 전기로에 의한 열 산화법에 의해 SiO$_{2}$(88[.angs.])와 ONO(89[.angs.])를 성장시켜 MIS capacitor를 제작한 후, 초 박막 유전체/실리콘 계면에서 전자파 간섭 효과를 실험적으로 비교 검토한 것이다. EWIE현상의 결과로서 첫째. 저 전계영역에 비해 고 전계영역에서 우세하며 둘째. SiO$_{2}$에 비해 ONO가 약하게 나타난다. 그러므로 ONO가 SiO$_{2}$보다 열 전송자 효과에 대한 저항성이 우수함을 알 수 있고 ULSI급의 게이트 절연막으로서의 실용가능성을 확인하였다.

• 한국진공학회지
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• 제4권S1호
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• pp.81-86
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• 1995

Aluminum has been deposited selectively on TiN surfaces in the presence of Si, SiO2 from Dimethyethylamine Alane(DMEAA). The film properties of the deopsited AI film were determined by various methods(SEM, Auger, UV-photospectrometer, Four point-probe, XRD). The effect of in-situ H2 plasma precleaning was studied. The effect of gap distance, pressure and temperature on the properties(crystallinity, resistance, grain size, morphology) of AI film and on the growth rates was investigated. It was found that the plasma precleaning promotes the growth rate and there exists optimum thmperature for maximum growth rate.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.41-44
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• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.279-282
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• 1999

Acceleration in integration density and speed performance of ULSI circuits require miniaturization of CMOS and interconnections as well as higher current density capabilities for transistors. A leading candidate to substitute A1-alloy is Cu, which has lower resistivity and higher melting point. So we can expect much higher electromigration resistance. In this paper, we are going to explain the major features of EM for MOCVD Cu according to variant conditions. We compared the life time and activation energy of MOCVD Cu with those of E-beam Cu and Al in The same conditions.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.107-113
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• 2003

Microelectronics device performance and its reliability are directly related to and controlled by its constituent materials and their microstructure. Specific processes used to form and shape the materials microstructure need to be controlled in order to achieve the ultimate device performance. Examples of front-end and back-end ULSI processes, packaging process, and novel optical storage materials are given to illustrate such process-structure-property-reliability relationship. As more novel materials are introduced to meet the new requirements for device shrinkage, such under-standing is indispensable for future generation process development and reliability assessment.

• 한국막학회:학술대회논문집
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• 한국막학회 1991년도 추계 총회 및 학술발표회
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• pp.17-26
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• 1991

It can be said that the current ULSI technology has been supported and/or accomplished by a major challenge to the clean room environment and the ultrapure water equipment manufacturers as to contamination control. The required improvement in ultrapure water quality, which is shown in Figure 1, would not have been possible without significant improvements in membrane performance and enhancements in analytical capabilities.

• 전자통신동향분석
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• 제4권2호
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• pp.110-123
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• 1989

ULSI는 대용량화, 고밀도화, 저소비전력화 및 고속 다기능화로 기술발전이 이루어 지고 있다. 기술추세에 의하면 90년 후반에 16MDRAM이 개발될 것으로 보인다. 여기에서 16MDRAM의 예상되는 패키지 형태를 알아본 결과 소비전력 50mW, 칩면적 $120mm^2$에 대응하는 SOJ형이 주로 쓰일것이며 재료로는 세라믹이 유망하다.