• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11C
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• pp.1102-1110
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• 2007

In this paper, we design the FPGA (Field-Programmable Gate Array) of the CAMB (Constant-Amplitude Multi-code Biorthogonal) modulation, and implement the SoC (System on Chip). The ASIC (Application Specific Integrated Circuit) chip is be implemented through targeting and board test. This 12Mbps modem SoC includes the ARM (Advanced RISC Machine)7TDMI, 64Kbyte SRAM(Static Random Access Memory) and ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter) for flexible applications. Additionally, the modem SoC can support the variable communication interfaces such as the 16-bits PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus) 1.1, and 16C550 Compatible UART (Universal Asynchronous Receiver/Transmitter).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.68-75
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• 2007

A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply which has dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna. The analog front end circuit of the proposed NFC transceiver consists of a transmitter and receiver of reader/writer block supporting NFC initiator or RFID reader mode, and a tag circuit for target of passive NFC mode or RFID tag mode. The maximum baud rate of the proposed NFC device is 212kbps by using UART serial interface. The chip has been designed and fabricated using a Magnachip's $0.35{\mu}m$ double poly 4-metal CMOS process, and the effective area of the chip is 2200um by 3600um.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.261-268
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• 2014

This paper presents a electrocardiogram(ECG), electromyogram(EMG), and Photoplethysmography(PPG) signal wireless monitoring system based on Bluetooth Low Energy (BLE). ECG and EMG sensor interface analog front-end circuits are designed by using off-the-shelf parts. Texas Instruments(TI)'s CC2540DK is used for BLE-based communication. Two CC2540DK modules are used as Peripheral and Central nodes. In peripheral device, vital signals are acquired by the analog front-ends and fed to ADC for analog-to-digital conversion. The peripheral transmitts the data through the air to the central device. The central device receive the data and sends them to PC using UART. GUI is designed using Labview for displaying the acquired vital signals. The developed system can be used for future ubiquitous wireless healthcare system based on bluetooth 4.0.

• Journal of Energy Engineering
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• v.20 no.4
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• pp.353-357
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• 2011

An embedded two-axis solar tracking system was developed by using AVR micro controller for enhancing solar energy utilization. The system consists of an Atmega128 micro controller, two step motors, two step drive modules, CdS sensors, GPS module and other accessories needed for functional stability. This system is controlled by both an astronomical method and an optical method. Initial operation is performed by the result from the astronomical method, which is followed by the fine controlled operation using the signals from Cds sensors. The GPS sensor generates UTC, longitude and latitude data where the solar tracker is installed. A database of solar altitude, azimuth, and sunrise and sunset times is provided by UART (Universal Asynchronous Receiver/Transmitter).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.809-812
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• 2013

This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform provided by Dynalith Systems consists of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. Design of Embedded system is executed in Flowrian2 of System Centroid Inc., in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.35-42
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• 2016

Various events of stop, playback, capture, and zoom-in/out in playing video is available in the monitor of a small size such as smart phones. However, if the size of the display increases, then the cost of the touch recognition is increased, thus provision of a touch event is not possible in practice. In this paper, we propose a video event control system that recognizes a touch inexpensively from the depth information, then provides the variety of events of the toggle, the pinch-in / out by the single or multi-touch. The proposed method finds a touch location and the touch path by the depth information from a depth camera, and determines the touch gesture type. This touch interface algorithm is implemented in a small single-board system, and can control the video event by sending the gesture information through the UART communication. Simulation results show that the proposed depth touch method can control the various events in a large screen.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1413-1421
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• 2014

This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform is consisted of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. design of Embedded system is executed in Flowrian II, in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.397-400
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• 2009

This paper describes ASIC design of Multimedia application SoC platform based RISC processor with BTB(Branch Target Buffer). For performance enhancement of platform, we use a simple branch prediction scheme, BTB structure, that stores a target address for branch instruction to remove pipeline harzard. Also, the platform includes a number of peripheral such as VGA controller, AC97 controller, UART controller, SRAM interface and Debug interface. The platform is designed and verified on a Xilinx VERTEX-4 FPGA using a number of test programs for functional tests and timing constraints. Finally, the platform is implemented into a single ASIC chip which can be operated at 100MHz clock frequency using the Chartered 0.18um process. As a result of performance estimation, the proposed platform shows about 5~9% performance improvement in comparison with the previous SoC Platform.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.1
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• pp.69-80
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• 2019

This paper proposes a multimodal sensor platform which supports plug and play (PnP) technology. PnP technology automatically recognizes a connected sensor module and an application program easily controls a sensor. To verify a multimodal platform for PnP technology, we build up a firmware and have the experiment on a sensor system. When a sensor module is connected to the platform, a firmware recognizes the sensor module and reads sensor data. As a result, it provides PnP technology to simply plug sensors without any software configuration. Measured sensor raw data suffer from various distortions such as gain, offset, and non-linearity errors. Therefore, we introduce a polynomial calculation to compensate for sensor distortions. To find the optimal coefficients for sensor calibration, we apply a genetic algorithm which reduces the calibration time. It achieves reasonable performance using only a few data points with reducing 97% error in the worst case. The platform supports various protocols for multimodal sensors, i.e., UART, I2C, I2S, SPI, and GPIO.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.1
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• pp.1-8
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• 2022

RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.