• Journal of Advanced Engineering and Technology
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• v.11 no.4
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• pp.267-271
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• 2018

A high-frequency therapy device with improved output by modifying a high-frequency stimulator was fabricated. The details of the design include generating part design, high-frequency transformer design, large output FET installation, DC voltage input part design and gate input driver design. Based on the real test using the pork meat, the temperature distributions according to the current electric transfer method, penetration depth, electrode diameter size were measured. In the CET method, the penetration depth was 0.5 cm and in the RET method, the penetration depth was 20 cm or more. In addition, it was confirmed that the temperature rise according to the penetration depth in the RET system was substantially constant, and the temperature rise was remarkable as the electrode diameter was small. As a result, it has been confirmed that the high frequency therapy device is highly affected by various conditions of the electrode.

• Journal of Sensor Science and Technology
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• v.31 no.4
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• pp.271-277
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• 2022

We analyzed the effects of the interface trap on the output characteristics of an inversion mode n-channel GaN Schottky barrier (SB)-MOSFET based on the N_it distribution using TCAD simulation. As interface trap number density (N_it) increased, the threshold voltage increased while the drain current density decreased. Under N_it=5.0×10¹⁰ cm^-2 condition, the threshold voltage was 3.2 V for V_DS=1 V, and the drain current density reduced to 2.4 mA/mm relative to the non-trap condition. Regardless of the N_it distribution type, there was an increase in the subthreshold swing (SS) following an increase in N_it. Under U-shaped N_it distribution, it was confirmed that the SS varied depending on the gate voltage. The interface fixed charge (Q_f) caused an shift in the threshold voltage and increased the off-state current collectively with the surface trap. In summary, GaN SB-MOSFET can be a building block for high power UV optoelectronic circuit provided the surface state is significantly reduced.

• Journal of Korean Port Research
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• v.9 no.1
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• pp.33-43
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• 1995

Korean economic and industrial structure has been seperated into some areas with the trend of the change to the bloc system of international economy: the Gyeongin including the capital area, the Middle-West, the South-West, the South-East, and the Eastern sea areas. Mokpo port has played a major role as the central one of the South-West area and the entrance of Yeong-san river of Jeonnam province gate. Some studies has been done on the Mokpo port, but there is no research of the analytical approach about it. In this paper, we analyze the data of 1994's on the domestic and oceangoing piers in the Mokpo port and simulate the transportation process of it through a queueing model. The results of the simulation are summarized as follows: The average arrival interval of the domestic vessel is 6.034 hours. The average service time and the berth utility rate are 24.056 hours and over 100%, respectively. The average arrival interval of the oceangoing vessel is 34.48 hours. The average service time and the berth utility rate are 120.04 hours and the 34.91%, respectively. The proposal to improving of the Mokpo port as follows: It is desirable to extend the capacity of domestic pier to about 50% for the optimal utility rate of 70% and in the case of oceangoing pier to be increase 65% of the vessel capacity for the optimal utility rate of 70%.

• Journal of IKEEE
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• v.28 no.2
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• pp.239-242
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• 2024

This paper proposed an ESD protection device that improved the current driving ability through Self-bias than the existing ESD protection device. The new proposed structure is based on the LRSCR structure and adds an N+ diffusion region, and reduces resistance by connecting the gate and the P+ diffusion region. As a result, it was confirmed that the proposed ESD protection device exhibits a trigger voltage of 11.8V and a holding voltage of 5.9V. It can be used in 5V applications for low voltage and is expected to have excellent current driving capability.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.170-170
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• 2010

Thin-film transistors (TFT) have become the key components of electronic and optoelectronic devices. Most conventional thin-film field-effect transistors in display applications use an amorphous or polycrystal Si:H layer as the channel. This silicon layers are opaque in the visible range and severely restrict the amount of light detected by the observer due to its bandgap energy smaller than the visible light. Therefore, Si:H TFT devices reduce the efficiency of light transmittance and brightness. One method to increase the efficiency is to use the transparent oxides for the channel, electrode, and gate insulator. The development of transparent oxides for the components of thin-film field-effect transistors and the room-temperature fabrication with low voltage operations of the devices can offer the flexibility in designing the devices and contribute to the progress of next generation display technologies based on transparent displays and flexible displays. In this thesis, I report on the dc performance of transparent thin-film transistors using amorphous indium tin zinc oxides for an active layer. $SiO_2$ was employed as the gate dielectric oxide. The amorphous indium tin zinc oxides were deposited by RF magnetron sputtering. The carrier concentration of amorphous indium tin zinc oxides was controlled by oxygen pressure in the sputtering ambient. Devices are realized that display a threshold voltage of 4.17V and an on/off ration of ${\sim}10^9$ operated as an n-type enhancement mode with saturation mobility with $15.8\;cm^2/Vs$. In conclusion, the fabrication and characterization of thin-film transistors using amorphous indium tin zinc oxides for an active layer were reported. The devices were fabricated at room temperature by RF magnetron sputtering. The operation of the devices was an n-type enhancement mode with good saturation characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.278-278
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• 2016

Solution-processed metal-oxide semiconductors have been considered as the next generation semiconducting materials for transparent and flexible electronics due to their high electrical performance. Moreover, since the oxide semiconductors show high sensitivity to light illumination and possess persistent photoconductivity (PPC), these properties can be utilized in realizing optical memory devices, which can transport information much faster than the electrons. In previous works, metal-oxide semiconductors are utilized as a memory device by using the light (i.e. illumination does the "writing", no-gate bias recovery the "reading" operations) [1]. The key issues for realizing the optical memory devices is to have high photoconductivity and a long life time of free electrons in the oxide semiconductors. However, mono-layered indium-zinc-oxide (IZO) and mono-layered indium-gallium-zinc-oxide (IGZO) have limited photoconductivity and relaxation time of 570 nA, 122 sec, 190 nA and 53 sec, respectively. Here, we boosted up the photoconductivity and relaxation time using a double-layered IZO/IGZO active layer structure. Solution-processed IZO (top) and IGZO (bottom) layers are prepared on a Si/SiO2 wafer and we utilized the conventional thermal annealing method. To investigate the photoconductivity and relaxation time, we exposed 9 mW/cm2 intensity light for 30 sec and the decaying behaviors were evaluated. It was found that the double-layered IZO/IGZO showed high photoconductivity and relaxation time of 28 uA and 1048 sec.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.291.1-291.1
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• 2016

Graphene by one of the two-dimensional (2D) materials has been focused on electronic applications due to its ultrahigh carrier mobility, outstanding thermal conductivity and superior optical properties. Although graphene has many remarkable properties, graphene devices have low on/off current ratio due to its zero bandgap. Despite considerable efforts to open its bandgap, it's hard to obtain appropriate improvements. To solve this problem, heterojunction barristor was proposed based on graphene. Mostly, this heterojunction barristor is made by transition metal dichalcogenides (TMDs), such as molybdenum disulfide ($MoS_2$) and tungsten diselenide ($WSe_2$), which have extremely thickness scalability of TMDs. The heterojunction barristor has the advantage of controlling graphene's Fermi level by applying gate bias, resulting in barrier height modulation between graphene interface and semiconductor. However, charged impurities between graphene and $SiO_2$ cause unexpected p-type doping of graphene. The graphene's Fermi level modulation is expected to be reduced due to this p-doping effect. Charged impurities make carrier mobility in graphene reduced and modulation of graphene's Fermi level limited. In this paper, we investigated theoretically and experimentally a relevance between graphene's Fermi level and p-type doping. Theoretically, when Fermi level is placed at the Dirac point, larger graphene's Fermi level modulation was calculated between -20 V and +20 V of $V_{GS}$. On the contrary, graphene's Fermi level modulation was 0.11 eV when Fermi level is far away from the Dirac point in the same range. Then, we produced two types heterojunction barristors which made by p-type doped graphene and graphene treated 2.4% APTES, respectively. On/off current ratio (32-fold) of graphene treated 2.4% APTES was improved in comparison with p-type doped graphene.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.169.1-169.1
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• 2015

최근 디스플레이 기술은 급속도로 발전해 가고 있다. 디스플레이 산업의 눈부신 성장에 발맞추어 초고화질, 초고선명, 고속 구동 및 대형화 등을 포함하는 최신 기술의 디스플레이 구동이 필요하다. 이러한 요구사항을 만족하기 위해서는 각 픽셀에 영상정보를 기입하는 충전시간을 급격히 감소시켜야 하고 따라서 픽셀 트랜지스터(TFT)의 이동도는 급격히 증가해야 한다. 따라서 차세대 디스플레이 실현을 위해서 고이동도 특성을 구현 할 수 있는 신물질의 개발이 매우 중요하다. 현재 산화물박막트랜지스터는 차세대 디스플레이 실현을 위해 가장 주목받고 있으며, 실제로 산화물박막 트랜지스터의 핵심소재인 In-Ga-Zn-O(a-IGZO) 산화물의 경우 국내외에서 디스플레이에 적용되어 생산이 시작되고있다. 그러나 a-IGZO 산화물의 경우 이동도가 $5-10cm^2V{\cdot}s$ 수준이어서 향후 개발 되어질 초고해상도/고속구동 디스플레이 실현(이동도 $50cm^2V{\cdot}s$)에는 한계가 있다. 따라서 본 연구에서는 이를 해결 할 수 있는 'post-IGZO' 개발을 위해 In2O3에 Ga2O3를 조성별로 고용시켜 박막의 구조적, 전기적, 광학적 특성 및 TFT를 제작하여 특성 연구를 진행하였다. 조성은 In2O3에 Ga2O3를 7.5%~15% 도핑 하였으며, Sputtering을 이용하여 indium gallium oxide(IGO) 박막을 제작하였다. 박막은 상온 및 $300^{\circ}C$에서 증착 하였으며 증착 된 IGO 박막은 Ga=12.5% 까지는 In2O3에 Ga이 모두 고용되어 cubic In2O3 poly crystalline을 나타내는 것을 확인하였으며 Ga=15%에서 Gallium 관련 2차상이 확인되었다. Ga양이 변화함에 따라 박막의 전기적 특성이 조절 가능하였으며 이를 이용하여 IGO 박막을 30 nm 두께로 증착 하여 IGO 박막을 channel layer로 사용하는 bottom gate structured TFTs를 제작 하였다. IGO TFTs는 Ga=10%에서 on/off ratio ${\sim}10^8$, 그리고 field-effect mobility $84.8cm^2/V{\cdot}S$를 나타내며 초고화질, 초고선명 차세대 디스플레이 적용 가능성을 보여 준다.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.193-198
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• 2007

The NiSi is very promising candidate for the metallization in 60nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process window temperature for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5{\Omega}/{\square}$ and $3{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.83-88
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• 2002

To increase the device linearities and the breakdown-voltages of FETs, $Al_{0.25}$G $a_{0.75}$As/I $n_{0.25}$G $a_{0.75}$As/A $l_{0.25}$G $a_{0.75}$As partially doped channel FET(DCFET) structures are proposed. The metal insulator-semiconductor(MIS) like structures show the high gate-drain breakdown voltage(-20V) and high linearities. We propose a partially doped channel structure to enhance the device linearity to the homogeneously doped channel structure. The physics of partially doped channel structure is investigated with 2D device simulation. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range. bias range.