Acknowledgement
This paper was supported by Korea Evaluation Institute of Industrial Technology (KEIT) grant funded by the Korea Government(MOTIE)(RS-2024-00403586, Development of Reinforced Insulated High Reliability Integrated Power IC Technology including Digital Precision Control) and conducted with the support of the Compound Material-based Next Generation Power Semiconductor Technology Development Project of the Ministry of Trade, Industry and Energy and the Korea Institute for Industrial Technology Evaluation (RS-2022-00143842, "Single/Three-phase AC/DC Converter Smart Power IC using SiC MOSFET devices")
References
- M. Ker and C. Yen, "Investigation and design of on-chip power-rail ESD clamp circuits without suffering latchup-like failure during system-level ESD test," IEEE J. Solid-State Circuits, vol 43, no. 11, pp.2533-2545, 2008. DOI: 10.1109/JSSC.2008.2005451
- Y. Koo, K. Lee, K. Kim, and J. Kwon, "Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology," J. Microelectron, vol.40, no.6, pp.1007-1012, 2009. DOI: 10.1016/j.mejo.2009.01.001
- C. Lin and R. Chang, "Design of ESD protection device for K/Ka-band applications in nanoscale CMOS process," IEEE Trans. Electron Devices, vol. 62, no.9, pp.2824-2829, 2015. DOI: 10.1109/TED.2015.2450225
- O. Semenov, H. Sarbishaei, and M. Sachdev, "ESD protection design for advanced CMOS," in Proc. SPIE, pp.123-131, 2001.
- B. Song, K. Do, Y. koo, "SCR-Based ESD Protection Using a Penta-Well for 5V Applications," IEEE Journal of the Electron Devices Society, vol. 6, pp.691-695, 2018. DOI: 10.1109/JEDS.2018.2817636
- O. Quittard, Z. Mrcarica, F. Blanc, G. Notermans, T. Smedes, and H.van Zwol, "ESD protection for high-voltage CMOS technologies," in Proc. EOS/ESD Symp., pp.77-86. 2006.