• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.131-137
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• 2014

A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of $1385{\times}835{\mu}m^2$.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.5
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• pp.457-461
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• 2014

Using $0.18{\mu}m$ CMOS process silicon neuron circuit of the pulse type for modeling biological neurons, were designed in the semiconductor integrated circuit. Neuron circuiSt providing is formed by MOS switch for initializing the input terminal of the capacitor to the input current signal, a pulse signal and an amplifier stage for generating an output voltage signal. Synapse circuit that can convert the current signal output of the input voltage signal, using a bump circuit consisting of NMOS transistors and PMOS few. Configure a chain of neurons for verification of the neuron model that provides synaptic neurons and two are connected in series, were performed SPICE simulation. Result of simulation, it was confirmed the normal operation of the synaptic transmission characteristics of the signal generation of nerve cells.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.161-166
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• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.7
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• pp.62-68
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• 2014

We proposed a series connection-type superconducting fault current limiter(SFCL) using E-I core that can prevent the internal magnetic flux generation of cores during normal operation, and prevent the saturation of cores due to a sudden magnetic flux generation at the initial stage of fault occurrence while limiting the peak current. Through a short-circuit simulation experiment, we analyzed the operating status of the two superconducting elements and limiting characteristics according to the size of the fault current peak before and after the failure. Further, the double peak current limiting characteristics according to the winding directions as well as the current and the voltage of each coil were compared and analyzed.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.8
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• pp.1055-1063
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• 2014

Power losses of a 1-stage DC-DC converter and 2-stage DC-DC converter are compared in this paper. A phase-shift full-bridge DC-DC converter is considered as 1-stage topology. This topology has disadvantages in the stress of rectifier diodes because of the resonance between the leakage inductor of the transformer and the junction capacitor of the rectifier diode. 2-stage topology is composed of an LLC resonant full-bridge DC-DC converter and buck converter. The LLC resonant full-bridge DC-DC converter does not need an RC snubber circuit of the rectifier diode. However, there is the drawback that the switching loss of the buck converter is large due to the hard switching operation. To reduce the switching loss of the buck converter, SiC MOSFET is used. This paper analyzes and compares power losses of two topologies considering temperature condition. The validity of the power loss analysis and calculation is verified by a PSIM simulation model.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.6
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• pp.564-571
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• 2014

A single-stage current-balancing multi-channel light-emitting diode (LED) driver is proposed in this study. The conventional LED driver system consists of two cascaded power conversion stages, i.e., an isolation DC/DC converter and LED driver. LED driver is usually implemented with the same number of expensive boost converters as those of LED channels to tightly control the current through each LED channel. Therefore, its overall system size is not only bulky, but the cost is rather high. By contrast, the proposed LED driver system is composed of a single power stage with the DC/DC converter and LED driver merged. Although the current balancing circuit of the proposed LED driver requires only passive devices instead of expensive boost converters, all currents through multi-channel LEDs can be well balanced. Therefore, the proposed LED driver features a small system size, improved efficiency, and low cost. To confirm the validity of the proposed driver, its operation and performance are verified on a prototype for a 46" LED TV.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.1
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• pp.1-9
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• 2003

In this paper, prototype of high-power-factor single-stage electronic ballast for fluorescent lamp is designed and implemented. A new low cost single stage high power factor electronic ballast for fluorescent lamps is based on integration of two-boost converter and LC type high frequency resonant inverter. The proposed ballast is combined by simple construction, because full bridge rectifier diode is eliminated and simple control circuit is applied. Boost converter operate in the voltage of positive and negative half cycle respectively at line frequency (60㎐), operation in discontinuous conduction mode performs high power factor. The experimental results show the good performance as PF 0.99, THD 15.4%, and CF 1.65 at output 63.5〔W〕.

• Progress in Superconductivity
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• v.1 no.1
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• pp.31-35
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• 1999

We have fabricated and tested a simple circuit of the rapid single-flux-quantum(RSFQ) four-stage shift register using a single layer high-$T_c$ superconducting (HTS) $YBa_2Cu_3O_{7-x}$ (YBCO) thin film structure with 9 step-edge Josephson junctions. The circuit includes two read superconducting quantum interference devices(SQUID) and four stages. To establish a robust HTS RSFQ device fabrication process, we have focussed on the reproducible process of sharp and straight step-edge formation as well as the ratio of film thickness to step height, t/h. The spread of step-edge junction parameters was measured from each 13 junctions with t/h=1/3, 1/2, and 2/3 at various temperatures. We have demonstrated the simplified operation of the shift register at 65 K.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.902-911
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• 2003

Using InGaP/GaAs HBT power cells with a 2.0${\times}$20$\mu\textrm{m}$$^2$ emitter area of a unit HBT, a two stage MMIC power amplifier has been developed for IMT-2000 handsets. An active-bias circuit has been used for temperature compensation and reduction in the idling current. Fitting on measured S-parameters of the HBT cells, circuit elements of HBT's nonlinear equivalent model have been extracted. The matching circuits have been designed basically with the extracted model. A two stage HBT MMIC power amplifier fabricated using ETRI's HBT process. The power amplifier produces an 1-㏈ compressed output power(P$\_$l-㏈/) of 28.4 ㏈m with 31% power added efficiency(PAE) and 23-㏈ power gain at 1.95 GHz in on-wafer measurement. Also, the power amplifier produces a 26 ㏈m output power, 28% PAE and a 22.3-㏈ power gain with a -40 ㏈c ACPR at a 3.84 ㎒ off-center frequency in COB measurement.quency in COB measurement.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1549-1552
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• 2003

Semiconductor gas sensor using tin oxide as sensing material has been used to detect gases based on the fact that impedance of the sensing material varies when the gas sensor is exposed to the gases. This variation comprises of two parts. The first one is variation in resistance of the sensing material and the other is expressed in terms of the sensor capacitance variation. Normally, only variation of the sensor resistance is considered. In this paper, using AC measurement with a capacitor-coupled inverting amplifier circuit, both changes in the sensor resistance and variations in the sensor capacitance were investigated. These characteristics were represented as magnitude gain and phase shift of AC signal at a specific frequency after passing it through the sensor and the designed circuit. A two-stage artificial neural network, which utilized the information above, was employed to identify and quantify three combustible gases: methane, propane and butane. The network outputs were approximately proportional to concentrations of test gases with reasonable level of error.