• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1606-1616
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• 1989

In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.

• Journal of IKEEE
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• v.18 no.4
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• pp.586-592
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• 2014

In this paper, high efficiency power management IC(PMIC) with DT-CMOS(Dynamic threshold voltage Complementary MOSFET) switching device is presented. PMIC is controlled PWM control method in order to have high power efficiency at high current level. The DT-CMOS switch with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuit consist of a saw-tooth generator, a band-gap reference(BGR) circuit, an error amplifier, comparator circuit, compensation circuit, and control block. The saw-tooth generator is made to have 1.2MHz oscillation frequency and full range of output swing from supply voltage(3.3V) to ground. The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on current mode PWM control circuits and low on-resistance switching device, achieved the high efficiency nearly 96% at 100mA output current. And Buck converter is designed along LDO in standby mode which fewer than 1mA for high efficiency. Also, this paper proposes two protection circuit in order to ensure the reliability.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.8
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• pp.477-486
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• 2000

This paper presents Pspice modeling methods for spark gaps and ZnO varistors and describes the application for the two-stage surge suppression circuit which was composed of the nonlinear components. The simulation modelings of nonlinear components were conducted on the basis of the voltage and current curves measured by the impulse current with the time-to-crest of $1~50 \mus$ and the impulse voltage with the rate of the time-to-crest of 10, 100 and 1000 V/\mus$. The firing voltages of the spark gap increased with increasing the rate of the time-to-crest of impulse voltage and the measured data were in good agreement with the simulated data. The I-V curves of the ZnO varistor were measured by applying the impulse currents of which time-to-crests range from 1 to $50 \mus$ and peak amplitudes from 10 A to 2 kA. The simulation modeling was based on the I-V curves replotted by taking away the inductive effects of the test circuit and leads. The meximum difference between the measured and calculated data was of the order of 3%. Also the two-stage surge suppression circuit made of the spark gap and the ZnO varistor was investigated with the impulse voltage of $10/1000\mus$$mutextrm{s}$ wave shape. The overall agreement between the theoretical and experimental results seems to be acceptable. As a consequence, it was known that the proposed simulation techniques could effectively be used to design the surge suppression circuits combined with nonlinear components.

• Journal of Advanced Navigation Technology
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• v.8 no.2
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• pp.176-183
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• 2004

In this paper, two-stage low noise amplifier(LNA) for S-band is designed and implemented using ATF54143 HEMT of HP CO. In order to get noise figure and input VSWR to be wanted, it is considered input VSWR and noise figure simultaneously in matching-circuit designing. The fabricated two-stage low noise amplifier has the gain of 27.8dB, input VSWR and output VSWR under 1.5.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.72-80
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• 1996

This paper presetns the development of a SSPA operating at KU-band(14~14.5 GHz) in order of replace TWTA used in the terrestria transponder of a satellite communication. The driving stage of SSPA uses internally matched 2W, 4W, 8W FET and the power stage is coupled with two internally matched 8W FET by branch-line cominer. The SSPA is fabricated with oth the RF circuit and the bias circuitry operating temperature compensation, regulation and sequence on aluminum housing. The SSPA testing resutls implemented in this way show 24.8$\pm$1dB small-signal gain, 41dBm P1dB power, a typical two tone C/IM3, -33dBc with single carrier backed off 6dB from p1dB, and gain stability over temeprature (-30~50)$\pm$1dB.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.283-285
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• 2008

본 논문은 조명용 LED 구동 장치를 위한 새로운 방식의 Two-stage LED 구동 회로를 제안한다. 제안된 회로는 PFC Flyback 회로의 다중 출력을 이용하여 LED 구동 회로에 사용된 소자의 내압 저하가 가능하고, 기존의 Two-stage LED 구동 회로에 비해 높은 효율을 갖는다. 제안된 회로는 Universal Input에서 25W 이상 조명 장치에 적용되는 IEC61000-3-2 Class C 규제를 만족하고, Digital Dimming을 사용하여 넓은 범위의 휘도 조절이 가능하다. 본 논문에서는 제안 회로의 동작 원리를 설명하고, 시뮬레이션 및 LED에 실제 적용 실험하여 제안 회로의 유용성을 입증하였다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.10
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• pp.139-147
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• 1996

In this study a two-stage fast pulse generaor using magnetic switches is proposed. The scheme consist of a switch, an inductor and two pairs of capacitor and saturable inductors, a linear transformer. The basic principle and the operation are described using a set of given parameters. The main issue of the magnetic pulse genration scheme is the system efficiency. This study focuses on the system efficiency improvement using magnetic switches. The voltage compression ratio, energy transfer with respect to core area are investigated. The output voltage and transferred energy as a function of input voltage are also included. Also, an analysis and experiments are performed to verify the porposed topology by implementing a 10[J] class experimental circuit. The efficiency of the transferred energy a tload side is 82%.

• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.339-345
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• 2016

This paper presents a two-stage power amplifier MMIC using a $0.4{\mu}m$ GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of $2.0{\times}1.9mm^2$ and was mounted on a $4{\times}4$ QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.242-245
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• 2007

To improve the efficiency of PDP TV, it should minimize the power losses transpired during AC-to-DC power conversion and PDP driving process. Generally the input power supply for PDP driving employes a two-stage power factor corrected converter, and it independently consists of sustain driver, which has high power consumption. However, such a circuit configuration has a difficulty for the PDP market requires low cost. To alleviate this problem, a new circuit composition is presented. It integrates input power supply with sustain driver in a single power stack. The input power supply of the proposed circuit has a single-stage structure to minimize power conversion loss, and it directly supplies power to the sustain driver so as to reduce the system size and cost.